Temperature Effects in NAND Flash Memories: A Comparison Between 2-D and 3-D Arrays

Resnati, Davide; Goda, Akira; Nicosia, Gianluca; Miccoli, Carmine; Spinelli, A.S.; Compagnoni, Christian Monzio

doi:10.1109/led.2017.2675160

Cited by 53 publications

(20 citation statements)

References 19 publications

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“…Statistical data for RTN are shown in [320][321][322] and are presented in Figure 38 (left) for different temperatures. Note that the usual exponential distribution of amplitude appears, whose slope is greatly reduced with respect to planar technologies [299,323,324]. This is due not only to the larger cell size, but also to the different doping of the channel and nature of the electron conduction process in the subthreshold region: a uniform conduction over the channel area is expected in 3D cells [325], as opposed to a surface conduction in planar devices.…”

Section: Random Telegraph Noisementioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Random Telegraph Noisementioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…6. The current increase with temperature in the on-state is a typical signature of polysilicon conduction [7,25,26] and is due both to the reduction in trap occupancy and to the enhancement of thermionic emission at the grain boundaries [12]. This effect results in the increase in the Fig.…”

Section: Average Polysilicon Currentmentioning

confidence: 99%

“…The presence of grains separated by highly defective grain boundaries in the polysilicon channel of the strings introduces some relevant issues in the operation and in the reliability of the array. Among them, it is worth mentioning (i) a severe limitation to the string current, especially at low temperature [7]; (ii) transient instabilities in the string current, due to the dependence of the average occupancy of the traps at the grain boundaries on the bias history of the string [8][9][10]; (iii) variability in the cell threshold voltage ( V T ) and in its temperature dependence, due to the haphazardness in the configuration of the polysilicon grains [11,12]; (iv) the worsening of the amplitude statistics of random telegraph noise (RTN) affecting cell V T , due to the contribution to percolative channel conduction of the nonuniform inversion of the intra-grain and inter-grain regions [13][14][15][16][17][18][19]. The adoption of a thin annular channel instead of a full nanowire was demonstrated to be a successful solution to mitigate some of these issues [20,21].…”

Section: Introductionmentioning

confidence: 99%

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

et al. 2020

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In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

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“…RTN causes Vth instability of 3-D NAND flash memory during two consecutive read operations [34], which originates from the electron capture/release phenomena in memory cell defects of tunneling oxide and poly Si. Figure 9 shows the measured RTN statistics probability density distribution of the 3-D NAND flash memory for different ambient temperatures [15]. RTN not only widens the positive tail above the PV level, but also introduces a negative tail below the PV level [34], which significantly distorts the program Vth distribution.…”

Section: Rtn Effectmentioning

confidence: 99%

“…Despite the several advantages of 3-D NAND flash memory, its reliability degrades with the continued scaling down and introduction of multi-level cell (MLC) and triple-level cell (TLC) NAND flash memory technologies [13,14]. In particular, the transition from 2-D NAND flash memory to 3-D NAND flash memory has been raising many new challenges [15]. 3-D quad-level cell (QLC) NAND flash memory technology is a promising candidate for lower cost per bit and higher-density nonvolatile memory [16,17].…”

Section: Introductionmentioning

confidence: 99%

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Wang

Lun

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a simulation method to model the program Vth distribution of 3-D vertical channel TLC/QLC charge-trapping NAND flash memory. The program Vth distribution can be calculated by considering ISPP noise, WL-WL interference, and the RTN effect of tunneling oxide and poly Si, which are the major physical factors affecting the width of program Vth distribution. Then, the program Vth distribution shapes with different ISPP incremental voltage steps are compared, and the results are found to be consistent with the experimental results. Code and layer-dependent coupling coefficients of WL-WL interference in 3-D vertical channel NAND flash memory are considered. The effect of RTN on the program Vth distribution is comprehensively studied. The program Vth distribution of a WL is calibrated with the measurement, and a good agreement is obtained, validating the array program Vth distribution simulation method. The simulation method can help in improving the reliability of 3-D TLC NAND flash memory and provides guidance for the design and optimization of 3-D QLC NAND flash memory technology.

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Temperature Effects in NAND Flash Memories: A Comparison Between 2-D and 3-D Arrays

Cited by 53 publications

References 19 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

Modeling of program Vth distribution for 3-D TLC NAND flash memory

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