This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.
<span>This paper presents the hardware design of a 2-dimensional Hadamard transform used the in the rate distortion optimization module in state-of-the-art HEVC video encoder. The transform is mainly used to quickly determine optimum block size for encoding part of a video frame. The proposed design is both scalable and fast by 1) implementing a unified architecture for sizes 4x4 to 32x32, and 2) pipelining and feed through control that allows high performance for all block sizes. The design starts with high-level algorithmic loop unrolling optimization to determine suitable level of parallelism. Based on this, a suitable hardware architecture is devised using transpose memory buffer as pipeline memory for maximum performance. The design is synthesized and implemented on Xilinx Kintex Ultrascale FPGA. Results indicate variable performance obtained for different block sizes and higher operating frequency compared to a similar work in literature. The proposed design can be used as a hardware accelerator to speed up the rate distortion optimization operation in HEVC video encoders.</span>
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