HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations

Abstract

This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.

Design and implementation of fast floating point units for FPGAs

“…Current applications become more complex and require extensive Floating-Point (FP) calculations to satisfy the accuracy requirements. Digital Signal Processing (DSP) and image processing, wireless communications, and other industrial applications are examples of FPGA applications [1][2][3][4][5][6][7][8][9]. The requirement for speed is achieved using FPGA technologies and parallel distributed systems while accuracy is achieved by incorporating FP arithmetic in algorithms implementations [10][11][12][13][14].…”