Purpose
The purpose of this study is to propose a pulse width based, in-pixel, arbitrary size kernel convolution processor. When image sensors are used in machine vision tasks, large amount of data need to be transferred to the output and fed to a processor. Basic and low-level image processing functions such as kernel convolution is used extensively in the early stages of most machine vision tasks. These low-level functions are usually computationally extensive and if the computation is performed inside every pixel, the burden on the external processor will be greatly reduced.
Design/methodology/approach
In the proposed architecture, digital pulse width processing is used to perform kernel convolution on the image sensor data. With this approach, while the photocurrent fluctuations are expressed with changes in the pulse width of an output signal, the small processor incorporated in each pixel receives the output signal of the corresponding pixel and its neighbors and produces a binary coded output result for that specific pixel. The process is commenced in parallel among all pixels of the image sensor.
Findings
It is shown that using the proposed architecture, not only kernel convolution can be performed in the digital domain inside smart image sensors but also arbitrary kernel coefficients are obtainable simply by adjusting the sampling frequency at different phases of the processing.
Originality/value
Although in-pixel digital kernel convolution has been previously reported however with the presented approach no in-pixel analog to binary coded digital converter is required. Furthermore, arbitrary kernel coefficients and scaling can be deployed in the processing. The given architecture is a suitable choice for smart image sensors which are to be used in high-speed machine vision tasks.
This paper presents an analytical model for calculating the output voltage and the power efficiency of multi-stage multi-output (MSMO) DC-DC converters (DDC) that use charge pump cells for boosting the voltage. Various cases such as multioutput current consumption and its effects on the output voltage and the power efficiency are studied. Based on the model, a tapered design approach is proposed that can bolster the power efficiency and lower the output voltage drop of MSMO DDCs. Moreover, a charge-pump-based DDC is introduced and designed to verify the proposed model. Simulation results using a standard high-voltage 180-nm CMOS technology affirms the accuracy of the presented model.
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