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Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost. The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded performance in low-scaled transistor operation of future CMOS technology models. This paper is destined to give an overview of all the major fault-tolerance techniques and noise models proposed so far. Summing and analysing all this work, we have divided the literature into three categories and discussed their applicability in terms of proposing circuit design modifications, finding output error probability or methods proposed to achieve highly accurate simulation results.

Text detection in natural scene images for content analysis is an interesting task. The research community has seen some great developments for English/Mandarin text detection. However, Urdu text extraction in natural scene images is a task not well addressed. In this work, firstly, a new dataset is introduced for Urdu text in natural scene images. The dataset comprises of 500 standalone images acquired from real scenes. Secondly, the channel enhanced Maximally Stable Extremal Region (MSER) method is applied to extract Urdu text regions as candidates in an image. Two-stage filtering mechanism is applied to eliminate non-candidate regions. In the first stage, text and noise are classified based on their geometric properties. In the second stage, a support vector machine classifier is trained to discard non-text candidate regions. After this, text candidate regions are linked using centroid-based vertical and horizontal distances. Text lines are further analyzed by a different classifier based on HOG features to remove non-text regions. Extensive experimentation is performed on the locally developed dataset to evaluate the performance. The experimental results show good performance on test set images. The dataset will be made available for research use. To the best of our knowledge, the work is the first of its kind for the Urdu language and would provide a good dataset for free research use and serve as a baseline performance on the task of Urdu text extraction.

Summary Real time cloud computing applications require a low latency network. The latency of optical interconnect in Data Center Networks (DCNs) is dependent on the complexity of the routing algorithm. The routing algorithm makes decisions about the forwarding of a packet on each successive node. If a routing algorithm is more complex, it requires more hardware resources to implement, which incurs extra cost and latency to the optical interconnect. This paper analyzes the complexity of existing architectures for the first time by showing Big O notation of complexity for each architecture. Different factors affecting the computational complexity of any routing algorithm are identified. This paper proposes a new architecture named VLCC. It has very low fixed routing complexity irrespective of network size. It has no packet loss at the network layer under many to many and all to one communication pattern. The only packet loss is at the physical layer due to signal degradation caused by optical components. The level of signal degradation is analyzed in terms of received signal power, bit error rate (BER), receiver sensitivity, path loss, and blocking probability. VLCC architecture is highly suitable for real time applications that require deterministic quality of service (QoS), where network performance is not affected by the traffic pattern.

This paper demonstrates the design procedure of a 4 × 8 phased array antenna. Initially, a unit element in multilayer topology with orthogonal slots in the ground plane to couple electromagnetic energy is designed. Then, a stacked patch with truncated edges is placed on the top thick substrate layer to enhance the bandwidth to 600 MHz. This multilayered stacked patch unit element is then used to design a 1 × 4 and 4 × 8 slot coupled stacked patch array. On the bottom side, a novel feedline structure is designed to provide a 90 o phase difference at the antenna feed for the circular polarization. The phase difference is achieved in the feedline structure using a quarter wavelength ( λg/4) difference in the lengths. After the numerical validation, both 1 × 4 and 4 × 8 stacked patch antenna arrays are fabricated to validate the simulations. The final 4 × 8 array achieved the target specification of an active reflection of less than −10 dB over 2.4 to 3.0 GHz, axial ratio of less than 3 dB, and stable radiation pattern over the complete band. In addition, beam scanning characteristics of the proposed stacked patch antenna arrays are also verified. The prototype resulted a peak gain of 19.5 dB at 2.7 GHz, 3‐dB beamwidth around 12 o in the xz‐plane, and scanning range of 90 o. Overall, good agreement between measured and simulated results showed that the proposed designed array capable of providing 600 MHz is an excellent candidate for the radar communication, small commercial drones, and synthetic aperture radar applications.