A. Yukawa scite author profile

AbstrwtA novel approach for a stable high-order delta-sigma modulator is presented. The modulator provides 16 bit resolution at 20kHz bandwidth using 4th~order noise shaping structure at an oversampling ratio of 64. The modulation loop is completely stabilized by an FIR prediction technique. The architecture inherently has less sensitivity to com¬ ponent mismatch. The total hardware is much the same as the noise shaping integrators.

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A 20 bit stereo oversampled D-to-A converter

Karuyama

Takeuchi

Sakurai

et al. 1993

IEEE Trans. Consumer Electron.

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A. Yukawa

A CMOS 8-Bit High-Speed A/D Converter IC

A 12 bit 5 &amp;mu;sec CMOS recursive ADC with 25 mW power consumption

A 16b Oversampling CODEC With Filtering DSP

An 8-bit 200 Ms/s 500 mW BiCMOS ADC

A stable high-order delta-sigma modulator with an FIR spectrum distributor

An oversampling A-to-D converter structure for VLSI digital codec's

A Stable 4th-Order Delta-Sigma Modulator with an FIR predictor

A 20 bit stereo oversampled D-to-A converter

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Product

Resources

About

A. Yukawa

A CMOS 8-Bit High-Speed A/D Converter IC

A 12 bit 5 &amp;amp;mu;sec CMOS recursive ADC with 25 mW power consumption

A 16b Oversampling CODEC With Filtering DSP

An 8-bit 200 Ms/s 500 mW BiCMOS ADC

A stable high-order delta-sigma modulator with an FIR spectrum distributor

An oversampling A-to-D converter structure for VLSI digital codec's

A Stable 4th-Order Delta-Sigma Modulator with an FIR predictor

A 20 bit stereo oversampled D-to-A converter

Contact Info

Product

Resources

About

A 12 bit 5 &mu;sec CMOS recursive ADC with 25 mW power consumption