PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory startingjiom a high level specification all the way down to layout. New techniques are used to perjform global optimisations across loop bowtdaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apartfrom the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm.
Abstract-Thispaper discusses improved force-directed scheduling and its application in the design of high-throughput DSP systems, such as real-time video VLSI circuits. We present a mathematical justification of the technique of force-directed scheduling, introduced by Paulin and Knight, and we show how the algorithm can be used to find cost-effective time assignments and resource allocations, allowing trade-offs between processing units and memories. Furthermore, we present modfications that improve the effectiveness and the efficiency of the algorithm. The significance of the improvements is illustrated by an empirical performance analysis based on a number of problem instances.
Abstract.This paper describes a new approach to high-level synthesis for high throughput applications. Such applications are typically found in real-time video systems such as HDTV. The method is capable of dealing with hierarchical flow graphs containing loops with manifest boundaries and linear index expressions. The algorithm is based on the model of periodic operations which allows optimizations across loop boundaries. Processing units and storage units are minimized simultaneously. The algorithm is implemented in the PHIDEO system. The major parts of this system are the processing unit synthesis, the scheduler and the memory synthesis including address generation.
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