This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (V
T) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (J
G). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-V
T: 1) conformal, lower-J
G ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.
We report on aggressively scaled RMG-HKL planar and multigate FinFET-based devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF 6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced J G and noise values can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF 6 , without EOT penalty; 2) SF 6 also enables improved mobility and reduced N it down to narrower fin devices (W Fin ≥5nm), mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while allowing a simplified dual-EWF metal CMOS scheme suitable for both device architectures and which maximizes the space for gate metallization; 3) PDA also yields lower PMOS |V T |, and substantially improved NBTI lifetime and hot-carrier (HC) immunity thanks to its reduction of bulk defects which is shown to be key in the (sub-)1nm EOT regime.
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