We investigate the 130nm (1.2V) and 280nm (2.5V) CMOS linear threshold voltage (Vtlin) and normalized saturation drain current (Idsat) versus channel width. Plots of Vtlin and Idsat versus channel width for different lengths are used to show the complex behavior as the channel width decreases. Both NMOS and PMOS Vtlin reach a maximum and then decrease as the width goes to W = 0.15um. NMOS Vtlin shows a 30% decease while PMOS Vtlin decreases 5% to 18%.
We then show that the Vtlin behavior is caused by two opposite factors, Shallow Trench Isolation (STI) y-stress effect and Inverse Narrow Width (INW) effect. We eliminate x-stress as a factor by designing all the transistors with Sa = 10um. We observe that NMOS and PMOS Idsat decrease as the width decreases from 20um to 1um reaching a minimum, after that Idsat increases again. We believe this Idsat behavior is also caused by two opposite factors, STI y-stress effect and Delta Width, DW effect. The Idsat behavior is different for NMOS and PMOS. The STI y-stress effect is less pronounced for short channel NMOS transistors while the DW effect is weaker for short channel PMOS transistors.Index Terms-delta width, DW, inverse narrow width, INW, STI mechanical stress, x-stress, y-stress.
We investigated the layout dependence effect that is caused by different active space, Sa, on 130nm CMOS transistors leakage current, loff. This layout dependence phenomenon is known as STI stress effect. The results show that when Sa changes from 5um to 0.34um, the NMOS loff decreases and the PMOS loff increases. The decrease of NMOS loff and increase of PMOS loff under compressive stress is similar to the trend of saturation current, Idsat but opposite the trend of linear threshold voltage, Vtlin. The layout dependence (or STI stress effect) not only affects the Vtlin and Idsat but also the loff of the 130nm CMOS transistors.
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