Munich, G e r m a n y THE DEVELOPMENT of MOS-RAMS evolved from the static memory cell with 8 or 6 transistors to the dynamic 4or 3-transistor cell and finally to the single-transistor cell 1.The decrease of the number of elements per cell thereby achieved allowed an increase in storage density.The single-transistor cell circuit shown in Figure 1 uses a transistor T for readlwrite selection and a capacitance Cs for storage. In contrast to the storage cells used until now, this cell has destructive readout since no amplifying device is used in the cell. During readout the voltage (e.g., VH for a stored "1") at the storage capacitor Cs is diminished by the distribution of the stored charge between the storage (Cs) and the digit line (CD) capacitance.Neglecting the parasitic capacitances, Cwl and C W~, of the selection transistor, the sensed quasi-dc voltage Vs isFor a reliable detection Vs must be outside of the undefined region with the width Vtr in which "0" and "1" cannot be discriminated by the senseirefresh amplifier. With this we get the condition. cS> CD (VHiVtr for the storage capacitance which determines primarily the cell area.To attain the required small cell area, a device with a high specific capacity, a digit line with low capacity CD and a sensitive refresh amplifier (low Vtr/VH) must be applied.Problems may arise from select noise by the parasitic capacitances Cw1, Cw2 of the selection transistor T. These problems can be eliminated by self-alignment gate techniques and noise-compensating devices.The requirements concerning the capacitances can be met by the cell in silicon-gate technology shown schematically in Figure 2 and in a realized version in Figure 3. In this layout the inversion layer under a silicon gate is used as electrode for the storage capacitor, resulting in a specific capacity of about 4 times the value of junction capacity.The leakage behavior of the depletion region around the inversion layer is closely related to that around a PN-junction 2.governs the capacitance CD, is made as short as possible by using the minimum period of the AI-word lines. The word line length per cell, (approximately 80 pm), is made larger to fit the sense/refresh circuit width.For the senselrefresh circuit, a two-terminal amplifier is well suited since no inversion of the polarity of the read signal is required to refresh the stored charge. The circuit proposed for this purpose ( Figure 4-realized layout Figure 5) is a gated flipflop which, if used as a symmetrical device, has the advanbge of being insensitive to technological tolerances, like other symmetrical integrated circuits.Further advantages of the gated flipflops in connection with two storage matrices (Figure 4) are: (a)-each of the two nodes can be used for a digit line (Figure 5), thus doubling the number of storage cells per amplifier. (b)-a starting voltage for sensing near the switching point of the flipflop can be easily achieved (precharging). (c)-the width Vtr of the undefined region of the sense/ refresh amplifier depends only on the s...
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