Storage array and sense/refresh circuit for single-transistor memory cells

Stein, K. U.; Sihling, A.; Doering, E.

doi:10.1109/jssc.1972.1052889

Cited by 61 publications

(3 citation statements)

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“…These currents are in the nA range for compound semiconductors because of FET leakage, while they are at fA levels for modern silicon DRAM cells. The high array density and simplicity of the 1T cell allows sophisticated clocked sense-amplifier designs in the periphery to more than compensate for the cell's shortcomings [108,109]. Onetransistor cell capacitors have evolved into highly vertical structures that are built either below (trench) or above (stack) the access transistor.…”

Section: Random Access Memory Cellsmentioning

confidence: 99%

“…A fully decoded low-array-power 1 kbit TSRAM prototype with DRAM-type high signal-to-noise-ratio sensing circuitry has been designed [68]. It features differential dynamic clocked sense-amplifiers [135] and a folded-bit-line architecture [146]. Ten address bits, plus row and column address strobe (RAS and CAS) inputs select a cell, while a write/read input sets the access mode.…”

Section: One-transistor Tsram Cellmentioning

confidence: 99%

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Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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Section: Random Access Memory Cellsmentioning

confidence: 99%

Section: One-transistor Tsram Cellmentioning

confidence: 99%