Two-dimensional arrays of silicon nanocrystals embedded in ultrathin
SiO2
layers for application in silicon nanocrystal memories were fabricated by a
three-step process: (a) growth of a tunnelling silicon oxide, (b) low pressure
chemical vapour deposition (LPCVD) of a thin layer of amorphous silicon
(α-Si), and (c) solid phase crystallization of the
α-Si layer in a high temperature furnace under nitrogen flow, followed by thermal oxidation
in the same furnace. Transmission electron microscopy (TEM) was used for the
structural characterization of the three-layer structure and the determination
of layer thicknesses and silicon nanocrystal size, while capacitance–voltage
(C–V) and
current–voltage (I–V) measurements were used to investigate the charging properties of the silicon nanocrystal
layer. In an attempt to increase the silicon nanocrystal density, as suggested in the
literature, a dip of the oxidized wafer in diluted HF before LPCVD deposition was used,
but this step was found to seriously affect the charging properties of the structure.
It was demonstrated in the literature that the use of self-aligned doubly-stacked Si dots improves retention characteristics of a nanocrystal memory. In this paper, we show that a similar effect may be obtained by using two distinct layers of silicon nanocrystals within the gate dielectric
of the MOS structure, if the nanocrystal density in each layer is high enough (above 1012 dots/cm2) so as to get an average effect of at least one smaller dot underneath each larger one. The relative distance of the layers and their position from the silicon substrate
and the gate metal are critical for optimum memory operation. Two different double-nanocrystal-layer structures were investigated. In the first structure the two nanocrystal layers were close together and they were composed of dots of different size (lower layer: 3 nm, upper layer: 5 nm),
while in the second structure the dot layers were composed of dots of equal diameter (d = 3 nm) and their inter-distance was much larger. In both cases, the retention characteristics of the structure were improved compared with a single dot layer structure. In the second case this improvement
was significantly larger than in the first case. Extrapolation of the data to ten years memory operation, showed that the charge loss after this time was only ≈ 12%.
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