Voids in ultrathin oxide and electron-beam lithography-patterned windows were used to deposit Ge selectively. The number of islands is a function of the total amount of Ge deposited in a void or window. Our results show that islands smaller than the void/window size nucleate mainly near the periphery. This might be due to the tensile strain in the Si substrate near the oxide edge. The interruption of the wetting layer reduces the loss of excitons by lateral diffusion, resulting in considerable increase in optical emission from islands.
Two-dimensional (2D) arrays of nanometre scale holes were opened in thin
SiO2 layers
on silicon by electron beam lithography and chemical etching. Oxidized silicon wafers with a 5 nm thick
SiO2
layer on top were used in this respect. Pattern transfer involved either only removal of
SiO2
or a two-step process of oxide removal and anisotropic silicon chemical etching to form
nanometre scale silicon V-grooves. The size of the holes in the photoresist layer varied in
the range 40–80 nm, depending on the exposure dose used. The smallest holes in the oxide
were about 50 nm in diameter, while in V-grooves the smallest width was nm. 2D arrays of Ge dots or Ge/Si hetero-nanocrystals were selectively grown on these
patterned silicon wafers. In small windows only one Ge island per hole was nucleated.
Gold-nanoparticle-coated K2SO4
microcrystals were prepared by a recently reported self-assembly process and their
organization onto micron-patterned silicon substrates was explored. Electron beam
lithography, anisotropic chemical etching and high temperature thermal oxidation were
used to fabricate oxidized or non-oxidized V-grooves on a silicon substrate and suspensions
of gold-coated microcrystals were spin-coated over the surface. The nanoparticle-coated
microcrystals were found to spontaneously deposit within the grooves and to form
remarkably coherent structures made up of lines of microcrystals aligned relative to
each other. Controls showed that this phenomenon was not observed with bare
K2SO4
crystals suggesting a catalytic role for the gold nanoparticles in the organization process.
This work was devoted to the development of a Ge quantum dot memory structure of a MOSFET type with laterally ordered Ge quantum dots within the gate dielectric stack. Lateral ordering of the Ge dots was achieved by the combination of the following technological steps: (a) use of a
focused ion beam (FIB) to create ordered two-dimensional arrays of regular holes on a field oxide on the silicon substrate, (b) chemical cleaning and restoring of the Si surface in the holes, (c) further oxidation to transfer the pattern from the field oxide to the silicon substrate, (d) removal
of the field oxide and thermal re-oxidation of the sample in order to create a tunneling oxide of homogeneous thickness on the patterned silicon surface, and (e) self-assembly of the two-dimensional arrays of Ge dots on the patterned tunneling oxide. The charging properties of the obtained
memory structure were characterized by electrical measurements. Charging of the Ge quantum dot layer by electrons injected from the substrate resulted in a large shift in the capacitance-voltage curves of the MOS structure. Charges were stored in deep traps in the charging layer, and consequently
the erasing process was difficult, resulting in a limited memory window. The advantages of controlled positioning of the quantum dots in the charging layer will be discussed.
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