A systematic study of the oxide reliability is presented in the thickness range 13.8 nm to 2.8 nm. It is demonstrated that (i) the time-tobreakdown should be extrapolated as a function of gate voltage for sub-5nm oxides, (ii) the temperature acceleration of timetobreakdown is drastically increasing with decreasing thickness, (iii) the combination of increased temperature acceleration. area scaling and low percentage failure rates leads to marginal intrinsic reliability for ultra-thin oxides, severely limiting further downscaling of oxide thickness. IntroductionGate dielectric reliability has always been a major issue determining the feasibility of MOS devices. The real reliability threat has always been the occurrence of defect-related extrinsic breakdown, while the intrinsic breakdown mode never posed any significant problem. However, as the conventionally used Si02 layer is scaled to thicknesses of only a few nanometers, several physical and statistical aspects of intrinsic breakdown change, (i) Less oxide "damage" is needed to trigger breakdown. (ii) The damage generation rate decreases strongly.(iii) The gate voltage rather than the oxide field determines the oxide breakdown [1,2], (iv) The statistical spread of the breakdown distribution increases [3].Furthermore, breakdown has become a less well-defined phenomenon:in sub-5 nm oxides, soft breakdown can occur and the question whether this corresponds to real oxide failure is still to be resolved [4]. In this paper, it is demonstrated that (i) the time-to-breakdown (Lao) should be extrapolated as a function of gate voltage for sub-5nm oxides. (ii) the temperature acceleration of tgD is drastically increasing with decreasing thickness. (iii) the combination of increased temperature acceleration, area scaling and low percentage failure rates leads to marginal intrinsic reliability for ultra-thin oxides, severely limiting the further downscaling of oxide thickness. Techniques and devices Capacitors were stressed with areas in the range 10' to IO" cm2 and oxide thicknesses (t,>J between 13.8 and 2.8 nm. Constant current stress (CCS) was applied for t,,,>4nm. constant voltage stress (CVS) for t,,,<4nm. All oxides were conventional furnace grown SO2, except for t,,,=3.5 and 2.8nm, which were nitrided in NO-ambient afier an initial oxidation. Since in small test structures (such as sub-micron transistors) the first breakdown is still the reliability limiting phenomenon [SI, all time-to-breakdowns in this work correspond to the first recorded breakdown phenomenon (soft or hard). A reliability spec of 0.01% failures after 10 years on 0.1 cm2 effective area was used in this study.Stress voltage dependence There have been many reports on the so-called polarity dependence of the CCS-Q,, for thin oxides (Fig. 1) [6]. However, if the tBD is plotted versus the applied gate voltage, this polarity gap disappears for sub5nm oxide, as shown in Fig. 2. This result demonstrates that the polarity gap is merely an artifact of the measurement, caused by a change in the parameters de...
Method for fabricating submicron silicide structures on silicon using a resistless electron beam lithography process Appl.A selfaligned cobalt silicide technology using rapid thermal processingThe thermal reaction of sputtered platinum with silicon to form platinum silicide by rapid thermal processing (RTP) has been investigated. A platinum film of 800 A was sputter deposited on un doped single-crystal silicon substrates. A wide range ofRTP cycles were used in N z ambient to study the formation kinetics and determine the phase growth sequence. The composition, thickness, impurity content, platinum-silicon interface quality, grain size, and surface oxide of the PtxSi y layer were characterized by Auger electron spectroscopy, transmission electron microscopy, and x-ray diffraction analysis. An the analysis techniques used were consistent in determining the platinum silicide system evolution. Initially, the reaction between platinum and silicon results in the fonnation of an intermediate phase of Pt 2 Si, the growth of which continues until the entire platinum fUm has been transformed into Pt 2 Si. Then the evolution of a final phase of PtSi starts at the Pt 2 Si/Si interface and the reaction between Pt 2 Si and Si proceeds towards the surface until the entire Pt z Si is converted to PtSi film. No simultaneous presence of the three phases, Pt, Pt z Si, and PtSi, was observed in any sample studied. An enhanced diffusion coefficient of Pt through Pt 2 Si was observed as a result of rapid thermal processing. It was detennined that 1 A ofPt results in the formation of 1.9 A of PtSi and 1 A of Si results in 1.44 A of PtSi. This small rate of Si consumption is desirable for silicidation of shallow junctions formation. The resistivity of PtSi was determined to be in the range 31-38 po. em which is similar to furnace annealed values. Reactive ion etchi.ng selectivity between silicon dioxide and PtSi was determined to be 33: 1. The high etching selectivity combined with small Si consumption make PtSi a potential candidate for submicron applications.
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