This paper presents a hardware implementation of multilayer feedforward neural networks (NN) using reconfigurable field-programmable gate arrays (FPGAs). Despite improvements in FPGA densities, the numerous multipliers in an NN limit the size of the network that can be implemented using a single FPGA, thus making NN applications not viable commercially. The proposed implementation is aimed at reducing resource requirement, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The sequential processing of the layers in an NN has been exploited in this paper to implement large NNs using a method of layer multiplexing. Instead of realizing a complete network, only the single largest layer is implemented. The same layer behaves as different layers with the help of a control block. The control block ensures proper functioning by assigning the appropriate inputs, weights, biases, and excitation function of the layer that is currently being computed. Multilayer networks have been implemented using Xilinx FPGA "XCV400hq240". The concept used is shown to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is proposed to make NN applications viable in terms of cost and speed for online applications. An NN-based flux estimator is implemented in FPGA and the results obtained are presented.
This study presents design and hardware implementation of cascade neural network (NN) based flux estimator using field programmable gate array (FPGA) for speed estimation in induction motor drives. The main focus of this study is the FPGA implementation of cascade NN based flux estimator. The major issues in FPGA implementation are optimisation of cost (resource) and execution time. A simple non-linear activation function called as Elliott function is used to reduce the execution time. To reduce the cost, and effectively utilise resource, the concept of layer multiplexing is adopted. The lowest bit precision needed for good performance of the estimator is identified and implemented. The proposed NN based flux estimator using simple excitation function and minimum bit precision is implemented using layer multiplexing technique. The designed estimator is tested on Spartan FPGA kit (3sd1800afg676-4) and the results obtained are presented.
Multilevel converter technology has recently emerged as a very important alternative in the area of high-power applications. Several modulation methods have been applied to multilevel Inverters. The modulation methods with higher switching frequency reduce filter size but increases switching losses. The Step modulation method operates with low switching frequency has less switching losses but it requires large filter size. To reduce the filter size the number of levels of the inverter is increased but it increases the cost of the system. This paper presents a novel modulation method where additional notches are introduced in the multi-level output voltage. These notches eliminate harmonics at the low order/frequency and shifts it a higher order/frequency and hence the filter size is reduced without increasing the switching losses and cost of the system. The proposed modulation method is verified through simulation and such results are also validated practically using a five-level Diode-clamped inverter prototype.
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