In this paper, we present an extensive study of leakage current mechanisms in diodes to model the dark current of various pixel architectures for active pixel CMOS image sensors. Dedicated test structures made in 0.35-m CMOS have been investigated to determine the various contributions to the leakage current. Three pixel variants with different photo diodes-n + /pwell, n + /nwell/psubstrate and p + /nwell/p-substrate-are described. We found that the main part of the total dark current is coming from the depletion of the photodiode edge at the surface. Furthermore, the source of the reset transistor contributes seriously to the total leakage current of a pixel. From the investigation of reverse current-voltage (-) characteristics, temperature dependencies of leakage current, and device simulations we found that for a wide depletion, such as n-well/p-well, thermal Shockley-Read-Hall generation is the main leakage mechanism, while for a junction with higher dope concentrations, such as n + /p-well or p + /n-well, tunneling and impact ionization are the dominant mechanisms. Index Terms-Image sensors, leakage currents, modeling. I. INTRODUCTION D ARK current is an important parameter to characterize the performance of an image sensor. Lowering the dark current will improve the dynamic range due to a reduction of the shot noise of the dark current. Furthermore, dark current reduction is correlated with a decrease of the fixed pattern noise and a reduction of the amount of white pixels defects in dark. Therefore, the reduction of dark current has been an important subject in the history of solid-state imagers. The main part of the work that has been reported by our department about this subject is related to dark current reduction in CCDs [1]-[4]. Nowadays, we use this knowledge to improve the technology and pixel architecture of image sensors made in Philips' 0.35-m CMOS imaging process. To optimize the performance of an active CMOS image pixel, its architecture and photo diode structure have to be optimized [5]-[7].
Abstract-This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buriedchannel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-μm CMOS process. The sensor characterization was carried out successfully, and the results show that, compared with a regular imager with the standard nMOS transistor surface-mode SF, the new pixel structure reduces dark random noise by 50% and improves the output swing by almost 100% without any conflicts to the signal readout operation of the pixels. Furthermore, the new pixel structure is able to drastically minimize in-pixel random-telegraph-signal noise.Index Terms-Buried-channel source follower (BSF), CMOS image sensor (CIS), optimized row selector, random-telegraphsignal (RTS) noise, 4T-active-pixel sensor.
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