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This article proposes a hybrid optimization technique for optimal location and sizing of electric vehicle fast charging stations (EVFCSs) and renewable energy sources (RESs). The proposed hybrid optimization technique is the consolidation of recalling-enhanced recurrent neural network (RERNN) and Marine Predators Algorithm (MPA), hence it is called RERNN-m2MPA technique.Here, an enhanced MPA (m2MPA) is proposed. The major objective of this article is to energy loss reduction, voltage deviation of the power system network and minimization of the land cost with maximum weightage to serve maximum EV with minimum installation cost. The lessening of voltage Abbreviations: F l , load force; F r , rolling resistance force; F acc , acceleration force; S, area; m ev , m ess , mass of EV and ESS; ψ, solar irradiance random variable; μ, σ, mean and SD of solar irradiance; F f , fill factor; i z , output of solar module temperature current; i MPP , V module current at the maximum power point; i SC , short circuit current; t, solar module temperature; t a , ambient temperature; i SC , short circuit current of the module; S I , scale index; T, temperature of electrolyte; T f , electrolyte freezing temperature; i b , battery current; i dis , average current of the discharge battery module; D D , Deviation distance; i B , branch current; n B , total branch present in the network; V Bus T ð Þ, bus voltage at time period T; ABC, phases; W g , weightage of the location of EVCS; L c , total cost of all the EVCS; EV De Ve , required energy of EV at Vth vehicle; C Bat Ve , battery capacity of EV at Vth vehicle; SOC Arrival Ve , SOC Depart Ve , arrival SOC and departure SOC of Vth vehicle; E Ra Ve , electric range of Vth vehicle; D ET , each trip distance; D Rate , discharging rate in G2V mode; l EV Bus , load of EVCS; EV Arrival Ve

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Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

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