2010
DOI: 10.1063/1.3492837
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ZnO nanowire and mesowire for logic inverter fabrication

Abstract: We report on a ZnO-based logic inverter utilizing two field effect transistors (FETs), whose respective channel has different wire-diameters under a top-gate dielectric of poly-4-vinylphenol. One FET with nanowire (160 nm) channel displayed an abrupt drain current (ID) increase and fast ID saturation near its positive threshold voltage (Vth) while the other FET with mesowire (770 nm) showed a thin-film transistor-like behavior and a negative Vth. When the nanowire and mesowire FETs were, respectively, used as … Show more

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Cited by 19 publications
(22 citation statements)
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“…[40] The grown ZnO NWs were several tens of micrometers in length and ≈100 nm in diameter. Details about the synthesis of ZnO NWs are described elsewhere.…”
Section: Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…[40] The grown ZnO NWs were several tens of micrometers in length and ≈100 nm in diameter. Details about the synthesis of ZnO NWs are described elsewhere.…”
Section: Methodsmentioning
confidence: 99%
“…Details about the synthesis of ZnO NWs are described elsewhere. [40] The grown ZnO NWs were several tens of micrometers in length and ≈100 nm in diameter. The as-grown ZnO NWs were transferred from a sapphire substrate to a 285 nm thick SiO 2 /p + -Si substrate by using the drop-and-dry method with isopropyl alcohol solvent.…”
Section: Methodsmentioning
confidence: 99%
“…The ZnO NWs had been synthesized by carbon-thermal reduction method on sapphire substrate. [ 41 ] These NWs were cut off from sapphire substrate and dispersed into the isopropyl alcohol to make dispersion solution. To dispose the NWs on the substrate, the dispersion solution containing NWs was dropped and dried on the surface of oxygen plasma-treated substrate.…”
Section: Methodsmentioning
confidence: 99%
“…According to SEM images of Figure 5 a,b (and their insets), the diameter/or thickness difference is slightly noticed between 200 and 150 nm ZnO nanowires, although they are covered by dielectric and electrode in FETs. Since it is reported that reducing the ZnO nanowire diameter decreases the channel current and moves the threshold voltage of FET toward positive direction as well, [ 40,41 ] we prepared this set of h-CMOS inverter expecting a positive transition voltage from the device, which contains an enhanced-mode n-channel ZnO FET. Supporting Information Figure S4 nanosheet WSe 2 .…”
Section: Doi: 101002/adma201403992mentioning
confidence: 99%
“…[1][2][3] Among the numerous oxide semiconductors, ZnO has been widely used as channel layer in TFTs in recent years, [4][5][6] owing to its simple composition and expeditious fabrication. In order to accumulate a sufficient number of charges in the TFTs channel, the use of high-dielectric constant (k) materials is suggested, which leads to a reduction in the operating voltage.…”
mentioning
confidence: 99%