Zero-skew clock routing trees with minimum wirelength

Boese, Kenneth D.; Kahng, Andrew B.

doi:10.1109/asic.1992.270316

Cited by 156 publications

(90 citation statements)

References 6 publications

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“…During this phase, clock TSV locations are decided. Then, the classic DME algorithm [10] is used to synthesize the virtual clock network. Note that the intra-block-depth needs to be considered in DME algorithm to achieve the zero skew.…”

Section: Clock Network Estimationmentioning

confidence: 99%

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Ahn¹,

Kim²,

Li³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

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Section: Clock Network Estimationmentioning

confidence: 99%

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Ahn¹,

Kim²,

Li³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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“…For example, if flip-flops in a shift register are not clustered together in the same leaf cluster of the (buffer) topology, hold time violations are exceptionally 1 The observation in [13] is not new, e.g., the LP-and graph-based methods of [12] [19] [18] use skew optimizations ("useful skew" [21]) to improve system clock frequency. Kourtev and Friedman [17] use integer programming in a method for simultaneous skew scheduling and topology design.…”

Section: The Associative Skew Problemmentioning

confidence: 99%

“…As described in [1,3,8], the DME algorithm constructs an optimal ZST for a given topology. Our heuristic H3 extracts the topology of the optimal slice merging solution (H2).…”

Section: Heuristic H3: Dme-mergingmentioning

confidence: 99%

“…However, no clean and/or optimal techniques (a la DME) have emerged for topology design and route embedding in this less constrained regime. 1 …”

Section: Introductionmentioning

confidence: 99%

“…Notably, the Deferred-Merge Embedding (DME) algorithm [1,3,8] embeds internal nodes of a topology G via (i) bottom-up construction of a tree of merging segments, or merging tree, representing loci of possible placements of internal nodes in the ZST; and (ii) top-down…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

The associative-skew clock routing problem

Chen¹,

Kahng²,

Qu³

et al.

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

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We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative skew problem is easier to address within current EDA frameworks than useful-skew (skew-scheduling) approaches, and defines an interesting tradeoff between the traditional zero-skew clock routing problem (one sink group) and the Steiner minimum tree problem (n sink groups). We present a set of heuristic building blocks, including an efficient and optimal method of merging two zero-skew trees such that zero skew is preserved within the sink sets of each tree. Finally, we list a number of open issues for research and practical application.

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Steiner Tree Problems in VLSI Layout Designs

Cho

2001

Combinatorial Optimization

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Zero-skew clock routing trees with minimum wirelength

Cited by 156 publications

References 6 publications

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

The associative-skew clock routing problem

Steiner Tree Problems in VLSI Layout Designs

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