Zero-delay FPGA-based odd-even sorting network

Hematian, Amirshahram; Chuprat, Suriayati; Manaf, Azizah Abdul; Parsazadeh, Nadia

doi:10.1109/isci.2013.6612389

Cited by 15 publications

(3 citation statements)

References 8 publications

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“…4) Odd-Even Sort: Odd-even sort has the potential to reduce memory accesses and improve performance for KNN [8]. This algorithm consists of two phases, an even phase and an odd phase, in which pairs of elements in a dataset are compared and swapped.…”

Section: B Sorting Algorithms Used By Knnmentioning

confidence: 99%

“…Odd-even sort is similar, its alternating sorting steps are suitable for parallel platforms but require lots of resources. It is possible to minimize memory use with small datasets for both algorithms, however this is not applicable to machine learning applications and algorithms like KNN, doubly so here as a result of the limited resources of the low-cost FPGA platform [6] [8]. Additionally, both do not take advantage of the k parameter to reduce sorting operations, slowing KNN significantly.…”

Section: Hls Simulationmentioning

confidence: 99%

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An Efficient SDN Architecture for Smart Home Security Accelerated by FPGA

Gordon¹,

Park²,

Tushir³

et al. 2021

Preprint

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With the rise in Internet of Things (IoT) devices, home network management and security are becoming complex.There is an urgent requirement to make smart home network management efficient. This work proposes an SDN-based architecture to secure smart home networks through K-Nearest Neighbor (KNN) based device classifications and malicious traffic detection. The efficiency is further enhanced by offloading the computation-intensive KNN model to Field Programmable Gate Arrays (FPGA), which offers parallel processing power of GPU platforms at lower costs and higher efficiencies, and can be used to accelerate time-sensitive tasks. The proposed parallelization and implementation of KNN on FPGA are achieved by using the Vivado Design Suite from Xilinx and High-Level Synthesis (HLS). When optimized with 10-fold cross-validation, the proposed solution for KNN consistently exhibits the best performances on FPGA when compared with four alternative KNN instances (i.e., 78% faster than the parallel Bubble Sortbased implementation and 99% faster than the other three sorting algorithms). Moreover, with 36,225 training samples, the proposed KNN solution classifies a test query with 95% accuracy in approximately 4 milliseconds on FPGA compared to 57 seconds on a CPU platform.

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Section: B Sorting Algorithms Used By Knnmentioning

confidence: 99%

Section: Hls Simulationmentioning

confidence: 99%

An Efficient SDN Architecture for Smart Home Security Accelerated by FPGA

Gordon¹,

Park²,

Tushir³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…The process is repeated until the array elements are sorted, with Odd and Even Phases occurring in each iteration. We execute a bubble sort on odd indexed elements in the odd phase and an even phase bubble sort on even indexed elements [37]. This process is repeated for each alternating index (odd-even pair, evenodd pair) until no swapping operations are necessary and the array is sorted.…”

Section: Introductionmentioning

confidence: 99%

Designing an Efficient Hardware Accelerator for Data Sorting Integrated With a Risc-V

Preethi¹,

G²,

Augustine³

et al. 2022

INDJCSE

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In microprocessor architecture, amid a few blocks outcome of the optimized sorting algorithm has proved its impact on the results. Sorters can be implemented in domains that includes data centers, cloud computing servers for IoT applications. Sorters can be implemented on hardware, by deploying the developed sorter on Field Programmable Gate Array (FPGA). By contrasting factors like power consumption, implementation time, and implementation space with those of the proposed algorithm, it is possible to show the shortcomings of existing sorters like Bubble sort, Bitonic sort, and Odd-Even sort. This approves that the sorter with higher capability will perform better for sorting involving large numbers, this helps in designing of large-scale sorting for aforementioned applications. Few sorters were compared based on the parameters and it was concluded that comparison-free odd-even was having upper hand. Hence, the optimized sorter was implemented on the MicroBlaze, which is based on RISC-V architecture.

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