“Zeppelin”: An SoC for Multichip Architectures

Burd, Thomas D.; Beck, Noah; White, Sean; Paraschou, Milam; Kalyanasundharam, Nathan; Donley, Gregg; Smith, Alan; Hewitt, Larry; Naffziger, Samuel

doi:10.1109/jssc.2018.2873584

Cited by 42 publications

(37 citation statements)

References 6 publications

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“…In [25], the energy efficiency of Lakefield can be improved to 0.2 pJ/b, and the architecture can be configured for PC and mobile processors. In [28], the Chiplets were prepared with the most mature technology among all computing systems; however, the delay can be reduced to 0.6 ns/mm and the bandwidth can be improved to 527 GB/s through 3D integration. In [26], the interconnect pitch between µbumps can be reduced to 20 µm through 2.5D integration, and the maximum bandwidth reaches 1 TB/s.…”

Section: Discussionmentioning

confidence: 99%

“…Although the inter-chip communication based on mutual inductance simplifies the routing design; however, electromagnetic coupling in a small volume leads to signal timing deterioration; therefore, this method requires a sufficient shielding design, which can increase the design difficulty. Burd et al [28] proposed the infinity fabric (IF) technology to connect Chiplets for higher scalability and configurability in a computing system. It combines scalable data fabric (SDF) and scalable control fabric (SCF) as a critical enabler and utilizes 3D package routing layers to support more complex connections.…”

Section: Computing Architecture Integrated With 3d Technologymentioning

confidence: 99%

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Architecture of Computing System based on Chiplet

et al. 2022

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Computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

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Section: Discussionmentioning

confidence: 99%

Section: Computing Architecture Integrated With 3d Technologymentioning

confidence: 99%

Architecture of Computing System based on Chiplet

et al. 2022

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“…Modern computer platforms require a large number of discrete voltage rails, often with multiple voltages required for a single component. For example, a CPU may require three separate voltage domains [5] while each channel of DDR4 DRAM requires two [46]. This means that for a basic two socket server system, there are a minimum of 14 required voltage regulators.…”

Section: Instrumentationmentioning

confidence: 99%

Enzian: an open, general, CPU/FPGA platform for systems software research

Cock

Ramdas

Schwyn

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Cache-coherent on-chip communication protocols currently in use include Intel's UltraPath Interconnect [32], AMD's scalable data fabric [33], IBM's Power9 on-chip interconnect [34], AMBA AXI Coherency Extensions (ACE) [8], AMBA5 Coherent Hub Interface (CHI) [35], and TileLink Cached (TL-C) [22]. ACE and TL-C are extensions of AXI and TL-UH, respectively.…”

Section: Related Workmentioning

confidence: 99%

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication

Kurth¹,

Rönninger²,

Benz³

et al. 2021

IEEE Trans. Comput.

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On-chip communication infrastructure is a central component of modern systems-on-chip (SoCs), and it continues to gain importance as the number of cores, the heterogeneity of components, and the on-chip and off-chip bandwidth continue to grow. Decades of research on on-chip networks enabled cache-coherent shared-memory multiprocessors. However, communication fabrics that meet the needs of heterogeneous many-cores and accelerator-rich SoCs, which are not, or only partially, coherent, are a much less mature research area. In this work, we present a modular, topology-agnostic, high-performance on-chip communication platform. The platform includes components to build and link subnetworks with customizable bandwidth and concurrency properties and adheres to a state-of-the-art, industry-standard protocol. We discuss microarchitectural trade-offs and timing/area characteristics of our modules and show that they can be composed to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end on-chip communication fabrics (not only network switches but also DMA engines and memory controllers) with high degrees of concurrency. We design and implement a state-of-the-art ML training accelerator, where our communication fabric scales to 1024 cores on a die, providing 32 TB/s cross-sectional bandwidth at only 24 ns round-trip latency between any two cores.

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“Zeppelin”: An SoC for Multichip Architectures

Cited by 42 publications

References 6 publications

Architecture of Computing System based on Chiplet

Architecture of Computing System based on Chiplet

Enzian: an open, general, CPU/FPGA platform for systems software research

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication

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