Yield and leakage current of organic thin-film transistor logic gates toward reliable and low-power operation of large-scale logic circuits for IoT nodes

Abstract

This paper reports on a strategy for yield improvement and static leakage current reduction by using a standard cell design for large-scale organic thin-film transistor (OTFT) circuits. Printable or flexible devices are suitable for IoT nodes, and digital OTFT circuits comprise the peripheral circuits of such devices. Sufficiently high yields and low static power consumptions are essential for battery operations of IoT nodes having functional digital circuits. Our design method to address the weak n-type OTFT on-current results in improved logic gate yields without any cell area increase. We improved the yield of the inverter, NAND, and NOR gates using a standard cell design, and achieved a 100%yield for the inverter and NOR gates and 88%yield for the NAND gates. Signal propagations with rail-to-rail operation were measured on test chips. Leakage currents of 585 pA and 2.94 nA were achieved for the inverter and NOR gates, respectively.

Measurement of 64 organic thin-film transistors in an array test structure using a relay-switch board for efficient evaluation of long-term reliability

“…An additional concern for early OTFT works was that the operation voltages of the OTFTs were a few tens of volts and consumed a large amount of power, thus lowering the operating voltage of the logic circuits composed of OTFTs is a focus of recent research. Considerable effort has been expended on lowvoltage operations of OTFT logic gates in the range of 5 V to 15 V. [20][21][22][23] Our past work included the low-voltage as a security component 24,25) with a 3.3 V operation and lowleakage current logic gates 26,27) with a 2.5 V operation.…”

“…44) This device 45) consists of an Al bottom gate electrode layer (gate), an AlO x insulator layer, a selfassembled monolayer (SAM), an organic semiconductor, and an Au top source or drain electrode. As the AlO x and SAM layers are sufficiently thin (4 nm and 2 nm thickness, respectively), devices operate at 3 V or lower, 27) which is the nominal operation voltage on printed carbon boards (PCB) or integrated circuit chips. Although we fabricated TFT devices in this paper with thermal deposition, the fabrication process can be replaced with printing technologies in the future as materials are developed and after considering compatibility with printing technologies.…”