XiSystem: a XiRisc-based SoC with reconfigurable IO module

Cappelli, Andrea; Lodi, Andrea; Bocchi, Massimo; Mucci, Claudio; Innocenti, M.; Bartolomeis, C. De; Ciccarelli, L.; Giansante, Roberto; Deledda, A.; Campi, Fabio; Toma, M.; Guerrieri, R.

doi:10.1109/jssc.2005.859319

Cited by 48 publications

(17 citation statements)

References 11 publications

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“…There have been numerous SDR solutions based on fine-grained computation fabrics. Examples of such solutions include picoArray [26], and the XiSystem's XiRisc [27]. The XiRisc, also includes a scalar/VLIW processor, with the reconfigurable logic acting as an accelerator.…”

Section: Wireless Baseband Processor Surveymentioning

confidence: 99%

From SODA to scotch: The evolution of a wireless baseband processor

Woh

Lin

Seo

et al. 2008

2008 41st IEEE/ACM International Symposium on Microarchitecture

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With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly changing wireless communication landscape. Software Defined Radio (SDR) promises to deliver a cost effective and flexible solution by implementing a wide variety of wireless protocols in software. In previous work, a fully programmable multicore architecture, SODA, was proposed that was able to meet the real-time requirements of 3G wireless protocols. SODA consists of one ARM control processor and four wide single instruction multiple data (SIMD) processing elements. Each processing element consists of a scalar and a wide 512-bit 32-lane SIMD datapath. A commercial prototype based on the SODA architecture, Ardbeg (named after a brand of Scotch Whisky), has been developed. In this paper, we present the architectural evolution of going from a research design to a commercial prototype, including the goals, tradeoffs, and final design choices.Ardbeg's redesign process can be grouped into the following three major areas: optimizing the wide SIMD datapath, providing long instruction word (LIW) support for SIMD operations, and adding application-specific hardware accelerators. Because SODA was originally designed with 180nm technology, the wide SIMD datapath is re-optimized in Ardbeg for 90nm technology. This includes re-evaluating the most efficient SIMD width, designing a wider SIMD shuffle network, and implementing faster SIMD arithmetic units. Ardbeg also provides modest LIW support by allowing two SIMD operations to issue in the same cycle. This LIW execution supports SDR algorithms' most common parallel SIMD execution patterns with minimal hardware overhead. A viable commercial SDR solution must be competitive with existing ASIC solutions. Therefore, algorithm-specific hardware is added for performance bottleneck algorithms while still maintaining enough flexibility to support multiple wireless protocols. The combination of these architectural improvements allows Ardbeg to achieve 1.5-7x speedup over SODA across multiple wireless algorithms while consuming less power.

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Section: Wireless Baseband Processor Surveymentioning

confidence: 99%

From SODA to scotch: The evolution of a wireless baseband processor

Woh

Lin

Seo

et al. 2008

2008 41st IEEE/ACM International Symposium on Microarchitecture

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“…[1,2,4]. Besides, data flow dominance is often exploited in coarse grain reconfigurable arrays (CGA) [7,8]. We have formerly proposed a hybrid CGA-SIMD processor made of 16 densely interconnected 64-bit 4-way SIMD units with shared and distributed register-files ( Figure 2) [9].…”

Section: ) a Monotonically Increasing Relation Between Precision Andmentioning

confidence: 99%

Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler

Bougard

Novo

et al. 2008

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

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The diversity and evolution of wireless communication standards are fast-pacing. This requires a wide-variety of baseband implementations within short time-to-market. Besides, always deeper submicron technology significantly increase design cost. This yields an increasing need for using reconfigurable or programmable solutions for an always larger part of wireless modems. Mapping the whole baseband functionality on a programmable architecture, as foreseen in tier-2 SDR, will become a must in future implementation. In handhelds where the multi-mode trend adds extra needs for programmability, the energy efficiency of SDR baseband is however a major concern. New processor architectures with major improvements on energy efficiency (GOPS/mW) are emerging but are still not sufficient to catch the continuously increasing complexity of wireless physical layers within the shrinking energy budget. To enable SDR in size, weight and power constrained devices, innovation is also needed at the software side. Specifically, a thorough architecture-aware algorithm implementation methodology is needed for the baseband signal processing functions, which account for most of the SDR computational complexity. We present the premise of such a methodology and illustrate its effectiveness on the design of key kernels from present and future wireless baseband systems. I INTRODUCTIONNowadays handhelds devices are integrating an increasing variety of wireless communication and connectivity standards, which depicts a multitude of operations modes. This diversity, combined with the increasing cost of silicon implementation, claims for flexible implementations wherever possible. The Tier-2 Software Defined Radio (SDR) approach, where the whole baseband functionality is run on programmable architectures, is an attractive way to obtain that flexibility. However, SDR typically comes with a lower energy efficiency than equivalent hardwired implementation. This energy gap remains to be filled in order to make SDR appropriate for size, weight and power constrained systems as handhelds are. Most SDR researches focus on reducing that gap by mean of more efficient processsor architectures. In [1-4], several processor-or multi-processor platform architectures are proposed with power consumption compatible with handhelds. Their performance however still prohibits the direct implementation of the most advanced standards (IEEE802.11n, 3GPP-LTE), with 100+Mbps throughputs and an increasing number of operations per bit.Besides computer architectures, innovation is also needed in the way baseband processing is handled in software, which has strong relations with signal processing. Typically, baseband signal processing algorithms are designed and optimized with a dedicated hardware (ASIC) implementation in mind, which requires regular and manifest computation structures as well as simple control flow, maximum functional blocks reuse and minimum data word width. Programmable architectures have other requirements. Typically, they can accommodate more complex con...

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“…In other approaches, data flow dominance is sometime exploited in coarse-grained reconfigurable arrays (CGA) [4,5]. The first class of architectures have tighter limitations in achievable throughput for a given clock frequency while the seconds have as main disadvantage to require very low level programming.…”

Section: Introductionmentioning

confidence: 99%

A coarse-grained array based baseband processor for 100Mbps+ software defined radio

Bougard

Sutter

Rabou

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

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The Software-Defined Radio (SDR) concept aims to enabling costeffective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication standards applying, e.g., multi-antenna transmission techniques, together with the reduced energy budget, is challenging SDR architectures. CoarseGrained Array (CGA) processors are strong candidates to undertake both high performance and low power. The design of a candidate hybrid CGA-SIMD processor for an SDR baseband platform is presented. The processor, designed in TSMC 90G process according to a dual-VT standard-cells flow, achieves a clock frequency of 400MHz in worst case conditions and consumes maximally 310mW active and 25mW leakage power (typical conditions) when delivering up to 25,. The mapping of a 20MHz 2x2 MIMO-OFDM transmit and receive baseband functionality is detailed as an application case study, achieving 100Mbps+ throughput with an average consumption of 220mW.

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XiSystem: a XiRisc-based SoC with reconfigurable IO module

Cited by 48 publications

References 11 publications

From SODA to scotch: The evolution of a wireless baseband processor

From SODA to scotch: The evolution of a wireless baseband processor

Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler

A coarse-grained array based baseband processor for 100Mbps+ software defined radio

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