Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages

Abstract

In this paper, we propose a new approach for the predictability and optimality of the inter-core communication and execution of tasks allocated on different cores of multicore architectures. Our approach is based on the execution of synchronous programs written in the ForeC programming language on deterministic architectures called PREcision Timed. The originality of the work resides in the time-triggered model of computation and communication that allows for a very precise control over the thread execution. Synchronization is done via configurable Time Division Multiple Access (TDMA) arbitrations where the optimal size and offset of the time slots are computed to reduce the inter-core synchronization costs. We implemented a robotic application and simulated it using MORSE, a robotic simulation environment. Results show that the model we propose guarantees time-predictable inter-core communication, the absence of concurrent accesses (without relying on hardware mechanisms), and allows for optimized execution throughput.

A Multi-Rate Precision Timed Programming Language for Multi-Cores

“…This section presents our implementation of Multi-Rate ForeC programs on a multi-core PRET architecture called MultiPRET [22], which consists of n FlexPRET [5] cores connected via a full cross-bar for inter-core communication (see Fig. 7).…”

“…The rates at which environment variables are read or written by external processes are outside the scope of this paper. More information can be found in [22]. Fig.…”