Worst Case Analysis of DRAM Latency in Multi-requestor Systems

Wu, Zheng Pei; Krish, Yogen; Pellizzoni, Rodolfo

doi:10.1109/rtss.2013.44

Cited by 81 publications

(88 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Instead of considering the memory system as a single resource, recent work [42] makes a more realistic assumption about the memory system, where the memory controller has one request queue per DRAM bank and one system-wide queue connected to the per-bank queues. That analysis, however, only considers the case where each processor core is assigned a private DRAM bank.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

177

158

View full text Add to dashboard Cite

Abstract-In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. We explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, we analyze the worstcase memory interference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.

show abstract

Section: Related Workmentioning

confidence: 99%

“…With bank sharing, memory requests can be re-ordered in the per-bank queues, thereby increasing memory request service times. The work in [42] unfortunately does not model this request re-ordering effect. In this paper, we have eliminated this limitation.…”

Section: Related Workmentioning

confidence: 99%

Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

177

158

View full text Add to dashboard Cite

show abstract

“…However, they indicate that the coherence is still an issue that has to be addressed. Similarly, several proposals for shared main memories deployed data isolation by assigning a private memory bank per core [19], [20]. However, we find that data isolation suffers from three limitations.…”

Section: Introductionmentioning

confidence: 88%

Predictable Cache Coherence for Multi-core Real-Time Systems

Hassan

Kaushik

Patel

2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

Abstract-This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We accomplish this by proposing a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on predictable MSI (PMSI) protocol. Our analysis shows that while the arbitration latency scales linearly, the coherence latency scales quadratically with the number of cores. We implement PMSI in gem5, and execute SPLASH-2 and synthetic multi-threaded workloads. Our empirical results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves average-case performance by up to 4× over the next best predictable alternative. PMSI has average slowdowns of 1.45× and 1.46× compared to conventional MSI and MESI protocols, respectively.

show abstract

“…This also applies to Shah (2012), where the WCET of transactions with fixed size is analyzed on an FPGA instance of a dynamically scheduled Altera SDRAM controller using an on-chip logic analyzer. In Wu et al (2013) and Krishnapillai et al (2014), a dynamically scheduled controller is presented that combines the notion of bank privatization with an open-page policy, which results in both low worst-case and average-case execution time. However, the analysis is limited to a single transaction size and memory map configuration, and the assumption that the number of memory requestors is not greater than the number of memory banks.…”

Section: Related Workmentioning

confidence: 99%

“…The latter can provide WCRT bounds and have lower average response times. However, they are limited in architecture or analysis to a single transaction size and memory map configuration (Paolieri et al 2013;Shah et al 2012;Choi et al 2011;Wu et al 2013;Krishnapillai et al 2014;Kim et al 2014), resulting in inefficiency for applications with variable transaction sizes. This article addresses the memory problem of mixed time-criticality systems by providing tight bounds on the execution time and response time for RT memory transactions, while at the same time providing low average execution time and response time for both RT and NRT transactions in systems with variable transaction sizes and different memory map configurations.…”

Section: Introductionmentioning

confidence: 99%

Architecture and analysis of a dynamically-scheduled real-time memory controller

Åkesson

Goossens

2015

Real-Time Syst

View full text Add to dashboard Cite

Memory controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a memory controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed memory controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.

show abstract

Worst Case Analysis of DRAM Latency in Multi-requestor Systems

Cited by 81 publications

References 13 publications

Bounding memory interference delay in COTS-based multi-core systems

Bounding memory interference delay in COTS-based multi-core systems

Predictable Cache Coherence for Multi-core Real-Time Systems

Architecture and analysis of a dynamically-scheduled real-time memory controller

Contact Info

Product

Resources

About