Wordline &amp; Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

Khellah, Muhammad; Ye, Y.; Kim, N.; Somasekhar, Dinesh; Pandya, G.; Farhang, A.; Zhang, K.; Webb, C.; De, Vivek

doi:10.1109/vlsic.2006.1705286

Cited by 58 publications

(21 citation statements)

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“…Due primarily to the scaling challenges of the SRAM transistors, such as random/intrinsic variations, the read/write characteristics of the SRAM bit-cells have been controlled by peripheral circuits: (i) for the read margin: hierarchical or short bit-lines and read-assist circuits [4][5][6][7], and (ii) for the write margin: write-assist circuits [8][9][10]. In using the read-assist circuits, the passgate disturbance can be reduced by decreasing the wordline voltage or the bit-line pre-charge voltage.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

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Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Shin

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability (V WL,OPT = 1.055 V) as well as to lower the minimum operating voltage for the read and write operations simultaneously (V MIN,READ = 0.58 V, V MIN,WRITE = 0.82 V for supply voltage (V DD ) = 1.1 V).

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Section: Measurement Results and Discussionmentioning

confidence: 99%

“…In [8][9][10], the lower bit-line pre-charge voltage (generated by a local regulator, n-type device's precharge, or pulse techniques) can suppress cell disturbance. The optimal bit-line voltage is about 70% to 80% of power supply voltage, due mainly to reverse stability limitations.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Shin

2014

JSTS:Journal of Semiconductor Technology and Science

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“…Also, there are serious concerns about the continued scalability of SRAM-based memories [3]. Several groups have proposed solutions to patch stability issues due to process variations in memory designs that use 6T SRAM cells [14,25].…”

Section: Related Workmentioning

confidence: 99%

Process Variation Tolerant 3T1D-Based Cache Architectures

Mutlu

Moscibroda

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

277

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“…SRAM cells with decoupled cell nodes from read bitlines have been widely accepted as an SRAM cell solution due to their improvement in cell stability [7][8][9][10][11][12][13][14][15]. Elimination of disturbing current from the read bitlines to the cell nodes makes the read-mode cell stability identical to the hold-mode stability.…”

Section: Introductionmentioning

confidence: 99%

“…A half-select-free wordline driver scheme and a write-back scheme were proposed at the cost of additional devices in each local wordline driver and data path [10,11]. To minimize the impact of the half-select problem without sacrificing too much silicon area, a pulsed wordline scheme has been proposed [12]. The pulsed wordline reduces the time period where SRAM cell nodes are disturbed, accordingly improving dynamic cell stability.…”

Section: Introductionmentioning

confidence: 99%