WLCSP parameter study for ball reliability analysis

Abstract

The technique of Wafer level chip scale package (WLCSP) is similar as flip chip packages without using underfill. The weakest point is solder joint reliability issue so the package size of WLCSP in current industry is used less than 10x10 mm 2 • In this paper, we use 5.5x5.5 mm 2 package size to take as test vehicle and focus on ball peeling and shear stresses to assume and simulate drop test and thermal cycling conditions. In this paper, several parameters including die size, re-distribution layer (RDL), polyimide (PI) material and thickness, under-bump metallization (UBM) structure and PI opening factors are discussed and taken as optimal design guidelines. Then, in order to verify simulation accuracy, we use 1500G peak acceleration and 1.0ms pulse duration time in board level drop test ·and consider thermal loading interval from 125°C to -40°C in JEDEC thermal cycling test (TCT) to analyze design factor influence compared to simulation trend chart.In the conclusion of this paper, focus on ball shear stress analysis, the obvious factors are RDL, UBM structure and PI opening and minor factors are die size, PI material and thickness. WLCSP with RDL can reduce 41 % shear stress than without one. The thicker UBM and smaller PI opening (210 urn -> 70 urn) can reduce 26% and 24% shear stress, respectively. However, focus on .ball peeling stress analysis, the obvious factors are RDL, UBM structure and PI thickness and minor factors are die size, PI material and opening. WLCSP with RDL can reduce 22% peeling stress than without one. The thinner UBM and thicker PI (5 urn -> 10 urn) can reduce 23% and 24% peeIng stress, respectively.

Board level WLCSP 3D thermal stress analysis by submodeling of FEA

“…The die, PCB, polyimide, passivation, under-bump metallization (UBM) and Cu pad are considered in the computational model. The assumptions in the FEM simulation are listed as below: (a) All materials except BT substrate are homogeneous and isotropic; (b) All material interfaces have perfect adhesion [1]. Owing to the ultra-thin thickness of UBM and passivation layers, the submodeling method was used in the finite element analysis to show the detail of stress distribution in the small structures near the solder joints.…”

“…WLCSP designs have been developed in the past few years with the demand in portable electronic devices and computers for smaller outlines, higher speed and multifunction. They have gained the momentum as attractive packaging solution for applications in integrated passive devices, flash memory, DRAM, and some of micro-controller devices [1]. Unlike lead frame, BGA, and flip chip in package, which all have either a metal or organic substrate as an interposer, the chip's pads connect directly to the PCB pads through individual solder balls, preferably with no post reflow applied underfill [2].…”

Investigation of solder creep behavior on wafer level CSP under thermal cycling loading

“…A lot of researches were done using various stress and strain indexes to enhance WLCSP solder ball reliability performance through structure design optimization. Tzeng et al studied silicon RDL, PI and UBM design using ball shear stress index for solder ball reliability analysis [2]. Liu …”