Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty

Kim, Ryan; Choi, Wonje; Zhuo, Chen; Pande, Partha Pratim; Marculescu, Diana; Mărculescu, Radu

doi:10.1109/tvlsi.2015.2512611

Cited by 37 publications

(19 citation statements)

References 30 publications

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“…In this paper, authors explore the paradigm of wireless NoC and demonstrate that by incorporating WiNoC, VFI, and dynamic V/F tuning synergistically, it can be designed energy-efficient multicore platforms without introducing noticeable performance penalty. The proposed approach can achieve between 5.7% and 46.6% EDP 2 savings over the state-of-the-art system and 26.8% and 60.5% EDP savings over a standard baseline non-VFI mesh-based system [15]. An adaptive multi-voltage scaling in WiNoC for high-performance, low power applications is proposed in [16].…”

Section: Related Workmentioning

confidence: 99%

Mind-Shift: An Method for Power and Energy Reduction inApplication Mapping onto Network-o-Chip architectures

Asadi

2021

Preprint

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Network-on-chip (NoC) is an efficient interconnection designing method for solving the limitations of buses in connecting IP cores. Power consumption is one of the most important issues in this area, solving this problem can lead to a more reliable and efficient design of NoC. Besides, there is another problem which is the More’s law is reaching an end. In this paper, we used a new approach, which improves designing points, so we can design NoC architecture more efficiently based on previous designs. Briefly, this method adds one step before the overall change of architecture which tests if the current design can be improved if we change some internal characteristics. For validation, we applied this method by using wire NoC, and changing its bottlenecks, and make them more efficient by using mapping and adding antennas for wireless communication. While this method seems simple at the first sight, but the result can help many designing, which are vital for industries, and technologies like Wireless Sensor Networks (WSN) and Internet of Things (IoT) devices. Briefly, this method can be used in NoC architectures and make them more efficient in a new style for new purposes. The results compared with the basic designing method with the new improved method; power and Energy improvements are respectively 25% and 46% with mapping and wireless improvements and approximately 60% more than traditional NoC in comparison with the basic method in this approach. This method also paves the way for green computing by avoiding producing more chemicals and products from a reusability perspective.

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Section: Related Workmentioning

confidence: 99%

Mind-Shift: An Method for Power and Energy Reduction inApplication Mapping onto Network-o-Chip architectures

Asadi

2021

Preprint

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“…However, this significantly complicates the voltage and frequency tuning, as a single decision must be made for the entire group of cores and communication links. Machine learning can be utilized here to help generalize a model that isn't obvious, to efficiently allocate the voltage and frequency of a VFI [19].…”

Section: 2) Dynamic Optimizationmentioning

confidence: 99%

Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis

et al. 2018

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“…Consequently, in this work, we use VFI as the suitable power management technique in 3D SWNoC and apply heterogeneous clustering (having different number of tiles for each cluster) for exploiting maximum benefits of VFI. The heterogeneous approach has been found to be more efficient than the homogeneous counterpart for enabling VFI-based power management (Kim et al 2016).…”

Section: Voltage Frequency Island-enabled 3d Nocmentioning

confidence: 99%

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Das

Doppa

Pande

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

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Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty

Cited by 37 publications

References 30 publications

Mind-Shift: An Method for Power and Energy Reduction inApplication Mapping onto Network-o-Chip architectures

Mind-Shift: An Method for Power and Energy Reduction inApplication Mapping onto Network-o-Chip architectures

Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

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