Wire placement for crosstalk energy minimization in address buses

Macchiarulo, L.; Macii, Enrico; Poncino, Massimo

doi:10.1109/date.2002.998264

Cited by 37 publications

(19 citation statements)

References 8 publications

(12 reference statements)

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“…Macchiarulo published the first work on spacing bus wires according to their switching activities [7]. An assumed extra amount of space is first distributed uniformly and then non-uniformly among the wires of an address bus.…”

Section: A Related Workmentioning

confidence: 99%

Wire Topology Optimization for Low Power CMOS

Zuber¹,

Bahlous

Ilnseher

et al. 2009

IEEE Trans. VLSI Syst.

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An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Nonuniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an industry-proven design flow. Wire power reductions of up to 9.55% for modern multiprocessor benchmarks with tight area constraints are demonstrated, twice as much as approaches that do not take switching activities into account. Timing is not adversely affected, and the yield limit is slightly improved.Index Terms-Interconnect topology optimization, low-power, switching activity driven, wire spacing.

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Section: A Related Workmentioning

confidence: 99%

Wire Topology Optimization for Low Power CMOS

Zuber¹,

Bahlous

Ilnseher

et al. 2009

IEEE Trans. VLSI Syst.

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“…In the literature there are presented two approaches that have the purpose to reduce parasitic capacitance. The first method try to reduce the physical value of the parasitic capacitance by increasing the distance between the traces (the distance between the traces doesn't have to be equal, [1]). Another approach is to reduce the number of switching that can appear between adjacent traces, and so reducing the number of coupling capacitance that are charge or discharge (physical implementation or coding of the information sent down the bus), [2].…”

Section: Introductionmentioning

confidence: 99%

Statistical information of crosstalk on parallel bus

Daraban

Pitica

2011

2011 IEEE 17th International Symposium for Design and Technology in Electronic Packaging (SIITME)

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There are lots of studies regarding methods of coding the information sent via a parallel data bus from inside a chip. As a result of shrinking the gadgets, the traces from an off-chip bus are getting closer, and the coupling capacitance is increasing. The traces from an off-chip bus are much longer than the ones from an on-chip bus, so a new study is necessary to analyze how crosstalk affects off-chip parallel data bus. The paper will take into account the capacitive coupling, but also the inductive coupling, which has bigger values for off-chip traces, affecting even more distant traces from the aggressor net. Additionally will be analyzed the effects of inter-symbol interference (ISI) on the crosstalk that appears between the traces of the parallel data bus. The study will show that methods used in coding theory for onchip busses can't guarantee an error free transmission.

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“…Related work that can be collectively called low-power bus layout optimization includes the permutation-based (PB) code [2], non-uniform wire placement [3], and a combination of the two [4]. Recently, a technique using a genetic algorithm and a fast optimization algorithm to minimize bus coupling energy was proposed [5].…”

Section: Introductionmentioning

confidence: 99%