Wideband envelope elimination and restoration power amplifier with high efficiency wideband envelope amplifier for WLAN 802.11g applications

Wang, F.; Kimball, D.; Popp, J.D.; Yang, A.T.; Lie, Donald Y. C.; Asbeck, P.M.; Larson, L.E.

doi:10.1109/mwsym.2005.1516688

Cited by 70 publications

(12 citation statements)

References 3 publications

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“…4 shows the amplitude PDF for a HSUPA signal and the corresponding optimum efficiency curves for standard LINC, ML-LINC, and AMO using 4 different supply levels. 1 The figure shows that ML-LINC increases the efficiency over a much wider power range than the standard LINC system, and AMO increases this range even further by effectively doubling the number of levels. Fig.…”

Section: B Multi-standard Efficiency Optimizationmentioning

confidence: 95%

“…Because power converter efficiency degrades dramatically as bandwidth increases, it is very difficult to achieve high efficiency for high data-rate communication standards. This is exacerbated by the 5-10x bandwidth expansion that occurs during the conversion from Cartesian to polar coordinates [1]. Thus this method is only practical for low-bandwidth systems.…”

Section: Conventional Approachesmentioning

confidence: 99%

“…AMO ARCHITECTURE Fig. 6 shows the AMO architecture, which consists of 1) predistorter for linearizing the combined nonlinearity 1 The PA efficiency curve was obtained from simulation, which will be described in Section V.…”

Section: B Multi-standard Efficiency Optimizationmentioning

confidence: 99%

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Asymmetric multilevel outphasing architecture for multi-standard transmitters

Chung

Godoy

Barton

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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We describe a new outphasing transmitter architecture in which the supply voltage for each PA can switch among multiple levels. It is based on a new asymmetric multilevel outphasing (AMO) modulation technique which increases overall efficiency over a much wider output power range than the standard LINC system while maintaining high linearity. For demonstration, the overall transmitter is simulated in a 65nm CMOS process with HSUPA and WLAN signals. The simulation results show an efficiency improvement from 17.7% to 40.7% for HSUPA at 25.3dBm output power and from 11.3% to 35.5% for WLAN 802.11g at 22.8dBm while still meeting system linearity requirements.

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Section: B Multi-standard Efficiency Optimizationmentioning

confidence: 95%

Section: Conventional Approachesmentioning

confidence: 99%

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Asymmetric multilevel outphasing architecture for multi-standard transmitters

Chung

Godoy

Barton

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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“…It demonstrates the use of non-linear component for linear amplification. In theory, it can achieve 100% efficiency and the total system efficiency is calculated by [119] ƞ 𝑡𝑡𝑜𝑜𝑡𝑡𝐷𝐷𝑡𝑡 = ƞ 𝑑𝑑𝑛𝑛𝑣𝑣𝑑𝑑𝑡𝑡𝑜𝑜𝑜𝑜𝑑𝑑 𝑃𝑃𝑃𝑃 . ƞ 𝑛𝑛𝑜𝑜𝑛𝑛−𝑡𝑡𝑖𝑖𝑛𝑛𝑑𝑑𝐷𝐷𝑟𝑟 𝑃𝑃𝑃𝑃 (4.10)…”

Section: Envelope Elimination and Restorationmentioning

confidence: 99%

“…Feipeng et al [119] compared their EER work with a class AB PA and the improvement of PAE is approximately doubled from 12.3% to 28%.…”

Section: Envelope Elimination and Restorationmentioning

confidence: 99%

An approach for circuit design optimization based on complexity considerations

Tan¹

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Optimizing circuit trade-offs is a highly challenging task for any design team. This challenge is further exacerbated with the additional design complexity of integrating multiple circuits. Today, with the increasing demand for newer wireless communication products, design teams face a shorter time-to-market (TTM) for every generation of their new products and each product requires major improvement in wireless capability. Hence, it is important for the design teams to design circuits with complexity in mind. A design approach divided into architecture complexity, component complexity and discretional complexity are proposed. A novel benchmarking figure-of-merit, complexity factor (CF), was formulated and proposed for the architecture complexity. A simulated application of a goal, gain optimization, demonstrated and revealed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for ultra-high frequency (UHF) applications. As the number of variables to be permuted is very high for the power amplifier (PA) blocks from circuit down to the process level, it is treated as a black box in the analysis but the next topology complexity step addressed this. A topology comparison was proposed between a 2-stacked EDNFET and SGNFET and a 4-stacked resistorladder SGNFET PA. Both of them achieved a near 20dBm output power and approximately 60% efficiency on the test-chips measurements, which demonstrated that the 2-stacked EDNFET and SGNFET topology with a reduction in stack height is a potential candidate for a reduced difficulty and complexity Doherty power amplifier (DPA) design. In the discretional complexity step, we explored the linearization of the DPA and proposed a DPA with a gm3 cancellation bias scheme tapping on its intrinsic linearization property, without adding external circuity to XII increase the complexity of the overall circuit but at the same time, improve its linearity by 6-8dB compared to a DPA optimized for power and more than 9dB compared with a balance PA with a similar structure. XIII

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Linearity and Efficiency Strategies for Next‐Generation Wireless Communications

Hueber

Staszewski

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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Wideband envelope elimination and restoration power amplifier with high efficiency wideband envelope amplifier for WLAN 802.11g applications

Cited by 70 publications

References 3 publications

Asymmetric multilevel outphasing architecture for multi-standard transmitters

Asymmetric multilevel outphasing architecture for multi-standard transmitters

An approach for circuit design optimization based on complexity considerations

Linearity and Efficiency Strategies for Next‐Generation Wireless Communications

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