Wideband and multiband CMOS LNAs: State-of-the-art and future prospects

Arshad, Sana; Zafar, Faiza; Ramzan, Rashad; Wahab, Q.

doi:10.1016/j.mejo.2013.04.011

Cited by 33 publications

(11 citation statements)

References 111 publications

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“…1), has been selected as a proof-of-concept due to its extensive use and benefits. In comparison with other single stages, cascode topology presents [33] a higher power gain, bandwidth [5], [34], and output impedance, with a lower consumption [35]. Fig.…”

Section: A Class a Pa Description And Layoutmentioning

confidence: 99%

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

Perpiñà

Reverter

León

et al. 2019

IEEE Trans. Instrum. Meas.

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 Abstract-The viability of using off-chip single-shot imaging techniques for local thermal testing in integrated Radio Frequency (RF) power amplifiers (PA's) is analyzed. With this approach, the frequency response of the output power and power gain of a Class A RF PA is measured, also deriving information about the intrinsic operation of its transistors. To carry out this case study, the PA is heterodynally driven, and its electrical behavior is down converted into a lower frequency thermal field acquirable with an InfraRed Lock-In Thermography (IR-LIT) system. After discussing the theory, the feasibility of the proposed approach is demonstrated and assessed with thermal sensors monolithically integrated in the PA. As crucial advantages to RF-testing, this local approach is noninvasive and demands less complex instrumentation than the mainstream commercially available solutions.

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Section: A Class a Pa Description And Layoutmentioning

confidence: 99%

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

Perpiñà

Reverter

León

et al. 2019

IEEE Trans. Instrum. Meas.

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“…It gives reasons for low-power very-large scale integration (VLSI) design industries and researchers to develop low-power, low-noise, and reliable UWB radio-frequency integrated circuits (RFICs) for these applications. Moreover, continuous shrinking in complementary metal oxide semiconductor (CMOS) chip fabrication technologies and split manufacturing techniques in RF designs [6,7], makes it possible to design and fabricate RFICs on the nanometer scale [8,9].…”

Section: Introductionmentioning

confidence: 99%

A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

Singh

Arya

Kumar

2018

JLPEA

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An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.

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“…In an SDR a large bandwidth is sampled in order to capture multiband services, reducing system size and cost (De Vito, 2013;Muñoz-Ferreras et al, 2011). The necessity for large bandwidth places stringent requirements on the ADC front-end and low speed ADCs are less suitable for such applications (De Vito, 2013;Arshad et al, 2013;Yuce et al, 2008). Flash ADCs provide the fastest sampling speeds and are therefore favored for applications such as SDR (Yuce et al, 2008).…”

Section: Introductionmentioning

confidence: 99%

High-speed Cherry Hooper flash analog-to-digital converter

Fauré

Sinha

2017

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Purpose -The 60 GHz unlicensed band is being utilized for high speed wireless networks with data rates in the gigabit range. In order to successfully make use of these high speed signals in a digital system, a high speed analog-to-digital converter (ADC) is required. This paper presents the use of a common collector (CC) input tree and Cherry Hooper differential amplifier to enable analog-to-digital conversion at high frequencies. Approach -The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The Cherry Hooper differential amplifier is modified to accommodate the low breakdown voltages of the technology node and used as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM's 130 nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) 8HP technology node. Measurements were carried out on test printed circuit boards (PCBs) and compared with simulation results. Findings -The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity (INL) and differential nonlinearity (DNL) was 0.33 least significant bits (LSBs). The prototype ADC had a figure of merit of 42 pJ/sample. Originality/value -The prototype ADC results showed that the group delay for the Cherry Hooper comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC Cherry Hooper ADC is capable of achieving an ENOB close to 1.18 for frequencies up to 2 GHz, with 180 mW total power consumption.

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Wideband and multiband CMOS LNAs: State-of-the-art and future prospects

Cited by 33 publications

References 111 publications

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

Output Power and Gain Monitoring in RF CMOS Class A Power Amplifiers by Thermal Imaging

A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

High-speed Cherry Hooper flash analog-to-digital converter

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