Wideband 0.18&amp;#x03BC;m CMOS VCO using active inductor with negative resistance

Szczepkowski, Grzegorz; Baldwin, Gerard; Farrell, Alison

doi:10.1109/ecctd.2007.4529765

Cited by 20 publications

(4 citation statements)

References 5 publications

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“…The maximum output power is −3.89 dBm, including a 4.7 dB loss due to implementation, and operates at 2.7 GHz under a 1.8 V power supply. Table 1 summarizes the measured performance Mathematical Problems in Engineering of the VCO and includes other reported performances, for the purpose of comparison [7][8][9][13][14][15][16]].…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The varactors limited the tuning range within 30% due to the maximum to the minimum capacitance ratio of the varactor and the parasitic effect [1][2][3]. Therefore, various techniques have been proposed to enhance the tuning range of VCOs, such as switched capacitor arrays [4][5][6][7][8], switched inductors [9][10][11], and tunable active inductors (TAIs) [12][13][14][15][16]. TAI is one of the good candidates due to its small size, high , widely tunable inductance, and large inductance compared to those of the spiral inductor [17,18].…”

Section: Introductionmentioning

confidence: 99%

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A Wide Tuning-Range CMOS VCO with a Tunable Active Inductor

Kao

Lee

Chiu

2015

Mathematical Problems in Engineering

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This study describes a wide tuning-range VCO using tunable active inductor (TAI) topology and cross-coupled pair configuration for radio frequency operation. The TAI used two feedback loops to form a cascode circuit to obtain more degrees of freedom for inductance value. The TAI-VCO was fabricated using a 0.18 μm CMOS technology. The coarse frequency tuning is achieved by TAIs while the fine tuning is controlled by varactors. The fabricated circuit provides an output frequency range from 0.6 to 7.2 GHz (169%). The measured phase noise is from −110.38 to −86.01 dBc/Hz at a 1 MHz offset and output power is from −11.11 to −3.89 dBm within the entire frequency range under a 1.8 V power supply.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Wide Tuning-Range CMOS VCO with a Tunable Active Inductor

Kao

Lee

Chiu

2015

Mathematical Problems in Engineering

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“…With the help of NIC circuits, the effect of the high input capacitance which restricts the bandwidth in PA's, can be highly reduced. This kind of NIC circuits generating negative resistance can also be used in the oscillator circuits to increase their tuning range [19]. Henceforth, any kind of circuits requiring broadband matching can be designed with this type of NIC circuit.…”

Section: Discussionmentioning

confidence: 99%

CMOS non-Foster Circuit Design Using 0.35μm BiCMOS Models by Cancelling the Parasitic Capacitances

Durukan¹,

Palamutcuogullari²

2022

World Congress on Electrical Engineering and Computer Systems and Science

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In this paper, an improved type of CMOS non-Foster circuit with the cross-coupled pair is proposed to produce negative resistance, negative capacitance and negative inductance in the frequency range between 100 MHz and 3 GHz. Non-Foster circuits are also called negative impedance converter (NIC) circuits. The proposed NIC circuit is designed to eliminate the gate-source parasitic capacitances of NMOS transistors which are the core elements of this cross-coupled topology with the help of on-chip inductors. The negative impedance conversion capability of the NIC circuit is shown analytically with the detailed mathematical formulations and proofs. The circuit is also simulated and verified in AWR Design Environment using 0.35µm BiCMOS transistor models comparatively for two cases with and without LC tank sub-circuit. The circuit is tested and verified with the loads of 50Ω resistance, 5 pF capacitance and 10 nH inductance to be converted negatively. The improvement in the negative impedance conversion rate of the NIC circuit is presented clearly with the impedance-frequency curves. The results show that the performance of the proposed NIC circuit is satisfactory with the help of gate-source parasitic cancellation. Additionally, the preliminary on-chip IC component placement of the NIC circuit using 0.35µm BiCMOS models is proposed for the realization and production.

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“…The power density 2 0 n i is proportion to A 2 as shown in (8). So as the periodic function D 2 is included in the ISF 2 rms * , the noise power ratio can be expressed as (9) and is proportion to 2 rms * . The optimum value of the noise power ratio can be derived, because 2 rms * is the function of W/L.…”

Section: A Phase Noise Introduced By Mos Channel Currentmentioning

confidence: 99%

A low phase noise wideband VCO in 65nm RF CMOS for low power applications

Zhou

2012

2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT)

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A wideband LC VCO used in low power and phase noise applications is described. A phase noise model is utilized for its lower phase noise design. A switched capacitor array, two power supply and substrate noise filters are involved in the circuit. The phase noise imported by the MOS channel current and tank less resistance is modeled to give approximate evaluation of the circuit performance. The circuit has been implemented in a standard 65 nm CMOS technology. The test result indicates that the frequency of the VCO is from 750 MHz to 1.5 GHz, and the phase noise is -125.84 dBc/Hz @1 MHz in 1.21GHz. The chip consumes less than 2.25 mW with 1.2 V power supply, and occupies 0.7 mm 2 areas.

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Wideband 0.18μm CMOS VCO using active inductor with negative resistance

Cited by 20 publications

References 5 publications

A Wide Tuning-Range CMOS VCO with a Tunable Active Inductor

A Wide Tuning-Range CMOS VCO with a Tunable Active Inductor

CMOS non-Foster Circuit Design Using 0.35μm BiCMOS Models by Cancelling the Parasitic Capacitances

A low phase noise wideband VCO in 65nm RF CMOS for low power applications

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