Why and How Controlling Power Consumption during Test: A Survey

Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Todri, A.; Virazel, Arnaud

doi:10.1109/ats.2012.30

Cited by 9 publications

(4 citation statements)

References 18 publications

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“…In gating methods the main source of excessive peak power during capture mode is the switching activities in gating elements when the mode changes from shift to capture mode or vice versa. Excessive peak power can be avoided by reducing the level of switching activity during test [3]. Therefore, the proposed structure is able to control peak power violations by reducing switching activities in other parts of scan cells.…”

Section: The Proposed Gating Scan Architecturementioning

confidence: 99%

“…Excessive average power affects not 2 VLSI Design only temperature increase but also temperature variations. These temperature variations may induce timing variations during test and, in some cases, may lead to test-induced yield loss [3]. In addition, intensive heat generated by high switching activity during the test process has negative influences on the circuit packaging cost to make the CUT tolerable to higher level temperature.…”

Section: Introductionmentioning

confidence: 99%

“…However, in practice, it was outlined in [1] that restricting the time window to just one clock cycle is not realistic enough since the power consumption within one clock cycle may not be large enough to elevate the temperature over the thermal capacity limit of the chip. As pointed in [3,4], excessive peak power dissipation comes with a high instantaneous current demand due to high switching activity during test application time which may cause power supply noise (PSN). The excessive noise may induce several phenomena as outlined below.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Scan Architecture for Low Power Scan-Based Testing

Naeini

Ooi

2015

VLSI Design

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Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.

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Section: The Proposed Gating Scan Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel Scan Architecture for Low Power Scan-Based Testing

Naeini

Ooi

2015

VLSI Design

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“…In gating methods, the main source of excessive peak power during capture mode is the switching activities in the gating elements when the mode changes from shift to capture mode or vice versa. Excessive peak power can be avoided by reducing the level of switching activity during testing [4]. Therefore, the proposed structure is able to control the peak power violations by reducing the switching activities in other parts of the scan cells.…”

mentioning

confidence: 99%

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini

Dass²,

Ooi

2017

JLPEA

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Abstract:Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology.

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