Whitespace redistribution for thermal via insertion in 3D stacked ICs

Wong, Eric; Lim, Sung Kyu

doi:10.1109/iccd.2007.4601912

Cited by 12 publications

(7 citation statements)

References 10 publications

(9 reference statements)

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“…The widths and heights of white space are determined by a binary search that finds the maximal width/height under the constraint that no block be placed beyond chip area. We also implemented the Mathematical Programming (MP) based algorithm described by Wong and Lim [8]. In our implementation, the CPLEX solver is used.…”

Section: Resultsmentioning

confidence: 99%

“…Constraint (8) ensures that any pair of blocks that have a horizontal relationship do not overlap with each other. Constraint (9) ensures that lx is the minimum reciprocal of linear power density.…”

Section: Iia Problem Formulationmentioning

confidence: 99%

“…Wong and Lim [8] describe a mathematical programming formulation that iteratively repels blocks from hot tiles. They only consider the closest block for each tile, and may ignore blocks with much higher power densities that are only slightly farther away.…”

Section: Introductionmentioning

confidence: 99%

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Integrated circuit white space redistribution for temperature optimization

Chen

Zhou

Dick

2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-Thermal problems are important for integrated circuits with high power densities. Three-dimensional stacked-wafer integrated circuit technology reduces interconnect lengths and improves performance compared to two-dimensional integration. However, it intensifies thermal problems. One remedy is to redistribute white space during floorplanning. In this paper, we propose a two-phase algorithm to redistribute white space. In the first phase, the lateral heat flow white space redistribution problem is formulated as a minimum cycle ratio problem, in which the maximum power density is minimized. Since this phase only considers lateral heat flow, it also works for traditional two-dimensional integrated circuits. In the second phase, to consider inter-layer heat flow in threedimensional integrated circuits, we discretize the chip into an array of tiles and use a dynamic programming algorithm to minimize the maximum stacked tile power consumption. We compared our algorithms with a previously proposed technique based on mathematical programming. Our iterative minimum cycle ratio algorithm achieves 35% more reduction in peak temperature. Our two-phase algorithm achieves 4.21× reduction in peak temperature for three-dimensional integrated circuits compared to applying the first phase, alone.

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Section: Resultsmentioning

confidence: 99%

Section: Iia Problem Formulationmentioning

confidence: 99%

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Integrated circuit white space redistribution for temperature optimization

Chen

Zhou

Dick

2011

2011 Design, Automation &Amp; Test in Europe

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“…Grid tiles not covered by blocks define deadspace. For m blocks overlapping with a particular tile Ξ, deadspace detection runs in O(m 2 ) time [29], which is not prohibitively expensive because typically m < 50. In the uniform clustering grid, tiles with insufficient aligned deadspace (< Ξ d min ) are marked as obstructed.…”

Section: Net Clusteringmentioning

confidence: 99%

“…Previous work in physical design often neglects design constraints and overhead associated with TSVs, especially their area footprint [3, 11, 21-23, 28, 32]. Some studies explicitly consider thermal TSV insertion but not signal TSVs [20,22,23,29]. Other studies incorporate signal and power TSVs in their flow, but sometimes ignore footprints of signal TSVs [18,19].…”

Section: Introductionmentioning

confidence: 99%

Assembling 2-D Blocks Into 3-D Chips

Knechtel

Markov

Lienig

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been slow. In addition to technology-related difficulties, industry experts cite the lack of a commercial 3D EDA tool-chain and design standards, high risk associated with a new technology, and high cost of transition from 2D to 3D ICs. To streamline the transition, we explore design styles that reuse existing 2D Intellectual Property (IP) blocks. Currently, these design styles severely limit the placement of Through-Silicon Vias (TSVs) and constrain the reuse of existing 2D IP blocks in 3D ICs. To overcome this problem, we develop a methodology for using TSV islands and novel techniques for clustering nets to connect 2D IP blocks through TSV islands. Our empirical validation demonstrates 3D integration of traditional 2D circuit blocks without modifying their layout for this context.

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Nutzung von klassischen IP-Blöcken in 3D-Schaltkreisen

Knechtel¹

2012

Entwurf Integrierter 3d-Systeme Der Elektronik

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Whitespace redistribution for thermal via insertion in 3D stacked ICs

Cited by 12 publications

References 10 publications

Integrated circuit white space redistribution for temperature optimization

Integrated circuit white space redistribution for temperature optimization

Assembling 2-D Blocks Into 3-D Chips

Nutzung von klassischen IP-Blöcken in 3D-Schaltkreisen

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