Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

State of the Art of Lead-Free Solder Joint Reliability

“…For mobile products, completing a drop test is a very important task. The package and the PCB are the same as those [18][19][20][21][22] for the thermal cycling test. The drop test setup is according to JEDEC Standard JESD22-B111 as shown in Fig.…”

“…Figure 37 shows a fan-out wafer-level package (13.42 mm  13.42 mm) with a very large silicon chip (10 mm  10 mm), which is lead-free (Sn3Ag0.5Cu) solder balled on a PCB as shown in Fig. 2 [18][19][20][21][22]. The finite element model is shown in Fig.…”

“…Thermal cycling is the most common test in solder joint reliability. For example, the solder joint reliability of a fan-out wafer-level package of a 10 mm  10 mm chip on a PCB [18][19][20][21][22], as shown in Fig. 2, subjected to thermal cycling has been reported.…”

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

“…Figure 21 schematically shows the top view and crosssectional view of the FOWLP structure shown in Fig. 18 for thermal analyses [79,80]. It can be seen that the chip size is The ambient temperature is assumed to be 25 C. The boundary condition on the top side and bottom side of the PCB and the top side of the chip is with a convective heat transfer coefficient, h ¼ 10 W/m 2 K, which is to imitate a natural convection condition.…”