Warpage and Stress Characteristic Analyses on Package-on-Package (PoP) Structure

Tzeng, Yuan Lin; Kao, Nicholas; Chen, Eason; Lai, Jeng Yuan; Wang, Yu Po; Hsiao, C.S.

doi:10.1109/eptc.2007.4469725

Cited by 20 publications

(4 citation statements)

References 3 publications

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“…PoP packaging technology has been continuously developed and improved over the past decade in several different aspects. (1) Stricter control of warpage [45,46]: Due to the decreasing proportion of the packaging shell to the chip size (increasing in area) and the further improvement of system integration, warpage has become a more prominent issue and thus needs to be controlled. (2) More advanced interconnection methods: To reduce signal interference and transmission delay, traditional WB has gradually been replaced by flip-chip and copper pillar technologies.…”

Section: Pop Structurementioning

confidence: 99%

Survey of Reliability Research on 3D Packaged Memory

Zhou

et al. 2023

Electronics

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As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.

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Section: Pop Structurementioning

confidence: 99%

Survey of Reliability Research on 3D Packaged Memory

Zhou

et al. 2023

Electronics

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“…The nominal dimensions of the TFBGA package are adopted from the design in Refs. [10,31]. A finite element (FE) model was constructed for warpage prediction.…”

Section: Implementation For Semiconductor Packaging Applicationmentioning

confidence: 99%

“…The nominal dimensions of the TFBGA package are adopted from the design in Refs. [10,31]. The TFBGA package was subjected to the EMC molding process at 175 °C, which was used as a stress-free temperature.…”

Section: Description Of Tfbga Packagementioning

confidence: 99%

“…The details of design variables are summarized in Table 3. The design spaces of the package dimensions and the material properties were defined by the values found in the literature: package dimensions in [31,[33][34][35][36][37][38][39] and material properties in [40][41][42][43][44][45]. The TFBGA package was subjected to the EMC molding process at 175 • C, which was used as a stress-free temperature.…”

Section: Description Of Tfbga Packagementioning

confidence: 99%

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Implementation and Performance Evaluation of a Bivariate Cut-HDMR Metamodel for Semiconductor Packaging Design Problems with a Large Number of Input Variables

et al. 2021

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A metamodeling technique based on Bivariate Cut High Dimensional Model Representation (Bivariate Cut HDMR) is implemented for a semiconductor packaging design problem with 10 design variables. Bivariate Cut-HDMR constructs a metamodel by considering only up to second-order interactions. The implementation uses three uniformly distributed sample points (s = 3) with quadratic spline interpolation to construct the component functions of Bivariate Cut-HDMR, which can be used to make a direct comparison with a metamodel based on Central Composite Design (CCD). The performance of Bivariate Cut-HDMR is evaluated by two well-known error metrics: R-squared and Relative Average Absolute Error (RAAE). The results are compared with the performance of CCD. Bivariate Cut HDMR does not compromise the accuracy compared to CCD, although the former uses only one-fifth of sample points (201 sample points) required by the latter (1045 sample points). The sampling schemes and the predictions of cut-planes and boundary-planes are discussed to explain possible reasons for the outstanding performance of Bivariate Cut HDMR.

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Parametric study of thermally induced warpage of FpBGA package using finite element methods

Chandana¹,

Kumar

2022

Materials Today: Proceedings

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Warpage and Stress Characteristic Analyses on Package-on-Package (PoP) Structure

Cited by 20 publications

References 3 publications

Survey of Reliability Research on 3D Packaged Memory

Survey of Reliability Research on 3D Packaged Memory

Implementation and Performance Evaluation of a Bivariate Cut-HDMR Metamodel for Semiconductor Packaging Design Problems with a Large Number of Input Variables

Parametric study of thermally induced warpage of FpBGA package using finite element methods

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