Survey of Reliability Research on 3D Packaged Memory

Abstract

As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.

A Study on the Reliability Evaluation of a 3D Packaging Storage Module under Temperature Cycling Ultimate Stress Conditions

“…At present, most researchers and scholars concerned with the reliability of 3D packaging memory are mainly focused on the two structures of package stacking and chip stacking; however, this paper adopts the cube package structure, which, due to expensive and long manufacturing cycles and restrictions, has been researched very little [27]. In addition, the magnitude of the applied test load conditions is extremely insufficient.…”