Warp Processors

Abstract

We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions, reimplements those regions as a custom hardware circuit in the FPGA, and replaces the software region by a call to the new hardware implementation of that region. While not all benchmarks can be improved using warp processing, many can, and the improvements are dramatically better than those achievable by more traditional architecture improvements. The hardest part of warp processing is that of dynamically reimplementing code regions on an FPGA, requiring partitioning, decompilation, synthesis, placement, and routing tools, all having to execute with minimal computation time and data memory so as to coexist on chip with the main processor. We describe the results of developing our warp processor. We developed a custom FPGA fabric specifically designed to enable lean place and route tools, and we developed extremely fast and efficient versions of partitioning, decompilation, synthesis, technology mapping, placement, and routing. Warp processors achieve overall application speedups of 6.3X with energy savings of 66% across a set of embedded benchmark applications. We further show that our tools utilize acceptably small amounts of computation and memory which are far less than traditional tools. Our work illustrates the feasibility and potential of warp processing, and we can foresee the possibility of warp processing becoming a feature in a variety of computing domains, including desktop, server, and embedded applications.

A Survey on Reconfigurable System-on-Chips

“…[28]) or as a dedicated hardware (e.g. [29]). The scheduler is in charge of managing the tasks and deciding when a task will be executed.…”

“…Most of existing reconfigurable SoCs (e.g. [5,32,33,35] and [29]) are based on sharedbus or crossbar interconnection infrastructures. However, some NoC-based reconfigurable SoCs (e.g.…”

“…[12-14, 30, 31, 40-64] and [65]); (iv) Fine-, and coarse-grained reconfigurable fabrics (e.g. [5, 6, 25-27, 32, 33, 35, 66-68] and [29]); and (v) Mapping method for reconfigurable architectures (e.g. [5,36] and [69]).…”

“…Some reconfigurable computing systems use a standard FPGA as a reconfigurable fabric (e.g. Zynq-7000 [32], Arria 10 [33], Warp [29] etc. ), some adopt CGRA (e.g.…”

Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration

“…Warp [17] is a family of processors that automatically extracts and compiles kernels to Field-Programmable Gate Array (FPGA). A typical Warp processor is a System on Chip (SoC) with a main processor for executing applications, a less powerful processor on which a lean FPGA compiler runs, a profiler and a custom FPGA.…”