2011
DOI: 10.1109/jstqe.2010.2089431
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Wafer-Testing of Optoelectonic–Gigascale CMOS Integrated Circuits

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Cited by 7 publications
(5 citation statements)
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“…Edge-coupled devices have the advantage of broadband optical response, but access to the waveguide is not available until after the chips have been singulated from the wafer. Since the mode size of a standard single-mode fiber (SMF) and the waveguide may differ significantly (typically a factor [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], either mode-size converters are required or sub-micron alignment may be needed, or a combination of both. Grating couplers couple out-of-plane to a near-vertical direction and are manufacturable in thin membranetype high-contrast waveguides, typically in Si-based integration technologies.…”
Section: Introductionmentioning
confidence: 99%
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“…Edge-coupled devices have the advantage of broadband optical response, but access to the waveguide is not available until after the chips have been singulated from the wafer. Since the mode size of a standard single-mode fiber (SMF) and the waveguide may differ significantly (typically a factor [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], either mode-size converters are required or sub-micron alignment may be needed, or a combination of both. Grating couplers couple out-of-plane to a near-vertical direction and are manufacturable in thin membranetype high-contrast waveguides, typically in Si-based integration technologies.…”
Section: Introductionmentioning
confidence: 99%
“…Multi-port optical testing probe-heads have been developed using MEMS technology [12], but this technology adds complexity and extra processing to fabricate extra mechanical structures for the alignment between the probe head and the optical interfaces. Single optical probe systems using 6-axis alignment translations stages [13] have been developed in combination with standard electrical probing systems [14], but these systems do not allow multi-port parallel testing and they require active alignment between the optical probe and the PIC.…”
Section: Introductionmentioning
confidence: 99%
“…Our goal is to demonstrate methods of creating highly scalable Si based electrode arrays and we accordingly uncouple their design from the packaging choice. But for highly-scaled 3-D probes aimed at in vivo headfixed recordings, we can draw on existing solutions used in the semiconductor probe card industry, where systems face even more complex packaging constraints and designs connect and route over 10,000 high-speed wires out from a small space to sophisticated test equipment [ 46 ]. The semiconductor industry roadmap also sets out to increase the maximum number of pins to around 50,000 by 2028 [ 47 ], with each connection supporting significantly higher bandwidth than a passive probe or active neural amplifier requires.…”
Section: Introductionmentioning
confidence: 99%
“…To this end, it identifies optical interconnects as a potential enabling technology. Recent reports relating to the monolithic fabrication of photo detectors, modulators and emitters on Si have given rise to the exciting prospect of combining optoelectronics and GSI in a highvolume manufacturing environment [8]. In fact, the domain which involves measuring the electrical quantity such as voltage or current, using optical methods is adopted to perform testing modern integrated circuits [9].…”
Section: Introductionmentioning
confidence: 99%