Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

Skordas, Spyridon; Tulipe, D.C. La; Winstel, Kevin; Vo, Tuan; Priyadarshini, Deepika; Upham, A.; Song, Dengyuan; Hubbard, Alex; Johnson, Richard W.; Cauffman, K.; Kanakasabapathy, Sivananda; Lin, Wei; Knupp, S.; Malley, Matthew; Farooq, Mukta; Hannon, R.; Berger, D.; Iyer, S. Sundar Kumar

doi:10.1109/ltb-3d.2012.6238091

Cited by 10 publications

(3 citation statements)

References 2 publications

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“…Three-dimensional integration using silicon direct bonding has been studied by organizations such as IBM, Freescale, etc. Face-to-face and faceto-back joining are both applicable [75][76][77][78]. A face-to-back joining process to stack a silicon-on-insulator (SOI) wafer to another wafer based on the IBM platform is schematically shown in Fig.…”

Section: Without Underfillmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

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Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

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Section: Without Underfillmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

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“…Another direct application of oxide-oxide bonding aims to combine with via-last integration to offer flexibility of wafer-level integration [3], thanks to advantages inclusive of reliable bonding interface, low temperature bonding process, high-throughput and less process induced thermal and mechanical stress as compared to other thermo-compression bonding approaches [4,5].…”

Section: Introductionmentioning

confidence: 99%

W2W permanent stacking for 3D system integration

Peng

Kim

Soules

et al. 2014

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)

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In this paper, we present advances in 300mm waferto-wafer (W2W) oxide-oxide bonding for high density 3D interconnect application. A CMOS compatible low temperature oxide-oxide bonding method has been developed which yields consistent void-free bonding. In addition, sub-micron W2W alignment accuracy has been demonstrated with standalone test materials using an integrated permanent bonding platform.

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“…In particular, low-temperature oxide wafer bonding renders wafer-scale 3DI a high throughput, high alignment accuracy, and a reliable (hermetic) bonding interface. [9,10] Furthermore, the associated bumpless interconnects enables a substantially high interconnect density for power distribution, signal transmission, and thermal dissipation. Prior work has demonstrated integration of two high-performance 45-nm SOI-CMOS embedded-DRAM wafers based on low-temperature oxide bonding to fit in the µP-on-3Dcache scheme in Fig.…”

Section: Introductionmentioning

confidence: 99%

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Lin

Faltermeier

Winstel

et al. 2014

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

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Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

Cited by 10 publications

References 2 publications

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

W2W permanent stacking for 3D system integration

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

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