Wafer level embedding technology for 3D wafer level embedded package

Kumar, Aditya; Dingwei, Xia; Sekhar, Vasarla Nagendra; Lim, San Hua; Keng, Chin; Sharma, Gaurav; Rao, V.S.; Kripesh, V.; Lau, John H.; Kwong, Dim‐Lee

doi:10.1109/ectc.2009.5074177

Cited by 45 publications

(15 citation statements)

References 8 publications

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“…Fracture rgy release ra per layer and y Study on T Zhaohui Chen Institute mold via (TMV oelectronic pa he major con eliability of th level packag simulation un rmal cycling used to calcula ion between t effects of the m e examined b de some guid lectronic pack and challeng n, miniaturizat 3D microelec V) is one of the high den packaging. TM nnection for packaging (P ng [1][2][3][4][5][6][7][8]. With memory, A integrated in the reliability its application n could be ch match of coe ng compound will be induce e delaminatio n the molding lding compou h will also V structure un ure penetrate se the popcorn per, the reliabi ed wafer leve est vehicle wa the moisture s. The moist und of TM ding and the the hydro-me e mechanics w ate of the de d molding com Due to the ymmetric fin mo-mechanica wn in Figure 3 ween the copp , the was investigated by design of experiment study.…”

Section: Reliability Stractmentioning

confidence: 99%

Reliability study on through mold via (TMV) for 3D microelectronic packaging under thermal and moisture loadings

Chen

Chong

Zheng

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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Section: Reliability Stractmentioning

confidence: 99%

Reliability study on through mold via (TMV) for 3D microelectronic packaging under thermal and moisture loadings

Chen

Chong

Zheng

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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“…Earlier development of EMWLP is only 2D integration [3].A new embedded package has been developed that can realize 3D integration with several development processes and materials evaluation and their solutions come out for EMWLP technology. [3,[4][5].…”

Section: Introductionmentioning

confidence: 98%

Low temperature dielectric material for embedded micro wafer level packaging

Rao

Wee

et al. 2009

2009 11th Electronics Packaging Technology Conference

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In this paper, we have developed the evaluation results of low cure temperature (less than 200 deg C) dielectric materials in terms of process ability and adhesion on SiN and mold compound substrates. The results showed that the low cure temperature dielectric materials have good adhesion on SiN and mold compound substrate. Integration of thin film passives like inductors, capacitors and band pass filters are also demonstrated on this mold compound wafer platform using electroplated Cu and low cure temperature dielectric material. Developed thin film passives on mold compound wafer platform have significantly improved the passives performances that are benchmarked against high resistivity silicon wafer (HiRSi). Reliability test vehicles are fabricated using Cu RDL, low cure temperature dielectric material and electroplated Cu UBM with SAC solder bump interconnects. A complete description of dielectric material evaluation for EMWLP, process development of thin film passive fabrication and multi-layer RDL integration on reconstructed mold compound wafer has been discussed.

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“…Compression molding is one packaging technique currently being considered in order to achieve large area die embedding. Compared to other process technologies such as film lamination, large area compression molding allows for precise dimensional control (mold thickness variation < 20 µm) [3]. Epoxy molding compounds (EMCs) are the most widely used molding materials for compression molding and their reliability is of crucial importance towards system functionality [4].…”

Section: Introductionmentioning

confidence: 99%

“…One important requirement of any wafer-level die embedding technology is the ability to produce a molded wafer on which subsequent wafer-level processes can be carried out with ease [3]. Consequently deformation resulting from intrinsic process stresses and a thermal expansion mismatch between the Si wafer and the EMC are of great concern in thin-film packaging (below 1mm in thickness).…”

Section: Introductionmentioning

confidence: 99%

Investigation of warpage in wafer-level Molding: Measurements and FE analysis

Farrugia

Grech

Casha

et al. 2015

2015 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)

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Novel 3D packaging technologies which require largearea mold embedding are being developed in order to achieve further minimization and cost reductions. Compression molding using epoxy molding compounds is one technique being considered for wafer-level encapsulation. However significant warpage in molded wafers is a critical issue which may hinder successive processes from being carried out. Cases of both symmetric (spherical) and asymmetric (cylindrical)-shaped warpage have been reported in wafer-level compression molding trials on blank wafers. This paper presents finite element models of the molded wafer, with and without embedded dies, which take into account the observed complex multi-state warpage characteristics. Molded wafer warpage measurements were carried out in order verify the applicability of the small and large deformation theories for layered plates, to deduce the cure shrinkage molding compound properties and to validate the finite element model of the molded blank wafer. The latter was used to analyze possible factors (nonplanar mold layer thickness, anisotropic wafer elastic properties) leading to asymmetric warpage. The numerical model will thus enable the prediction of the optimum process and material conditions for the warpage to be minimized together with the expected deformation of the molded wafer model with embedded dies. Keywords-3D packaging; wafer-level molding; asymmetric warpage; bifurcation; epoxy molding compound 2015 Symposium on Design Test Integration and Packaging of MEMS and MOEMS 978-1-4799-8625-5/15/$31.00 ©2015 IEEE

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Wafer level embedding technology for 3D wafer level embedded package

Cited by 45 publications

References 8 publications

Reliability study on through mold via (TMV) for 3D microelectronic packaging under thermal and moisture loadings

Reliability study on through mold via (TMV) for 3D microelectronic packaging under thermal and moisture loadings

Low temperature dielectric material for embedded micro wafer level packaging

Investigation of warpage in wafer-level Molding: Measurements and FE analysis

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