Wafer bonding of silicon wafers covered with various surface layers

Wiegand, M.; Reiche, M.; Gösele, U.; Gutjahr, Karsten; Stolze, D.; Longwitz, Ralf G.; Hiller, E.

doi:10.1016/s0924-4247(00)00420-9

Cited by 40 publications

(24 citation statements)

References 9 publications

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“…The validity of the equation was then tested by controlling the thickness of the debonding blade and the thicknesses of the wafer samples under test. [13][14][15][16][17][18][19][20][21][22][23][24][25] …”

Section: History and Establishment Of The Artmentioning

confidence: 99%

A Review of Hydrophilic Silicon Wafer Bonding

Masteika

Kowal

Braithwaite

et al. 2014

ECS J. Solid State Sci. Technol.

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Hydrophilically activated direct wafer bonding is a technique for gluelessly attaching oxide-coated wafers together. This ability is a vital step in the construction of many microelectronic and microelectromechanical (MEMS) devices. In particular this technique is widely used in the production of 3d interconnected devices due to the lack of interlayer. © 2014 The Electrochemical Society. [DOI: 10.1149/2.007403jss] All rights reserved.Manuscript submitted June 5, 2013; revised manuscript received December 9, 2013. Published February 3, 2014 This review covers the key papers relating to the theory, techniques and quantification of hydrophilically activated silicon wafer bonding. This begins with a review of the history and development of the art. Bond strength characterization is then reviewed followed first by models of physical deformation and then by plasma and radical activation techniques.In the interests of clarity and succinctness this review is not an attempt to exhaustively catalog all direct bonding wafer literature. Excluded are hydrophobic and UHV bonding, and the many papers applying bonding techniques to differing combinations of wafer materials. This paper concludes with a summery of the state of the art of direct wafer bonding and a summation of the current wafer-bonding model derived from the papers reviewed. History and Establishment of the Art

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Section: History and Establishment Of The Artmentioning

confidence: 99%

A Review of Hydrophilic Silicon Wafer Bonding

Masteika

Kowal

Braithwaite

et al. 2014

ECS J. Solid State Sci. Technol.

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“…In this case, one might have to resort to oxides prepared at low temperature ͑400°C and below͒ by means of chemical vapor deposition ͑CVD͒. 9 However, CVD oxides prepared at low temperature do not possess properties favorable for wafer bonding. In this work, we investigate the necessary surface preparations needed for successful bonding of CVD oxide wafers deposited at low temperature to thermal oxide wafer grown at high temperature for the above application.…”

mentioning

confidence: 99%

Low-Temperature Direct CVD Oxides to Thermal Oxide Wafer Bonding in Silicon Layer Transfer

Tan

Chen

Fan

et al. 2005

Electrochem. Solid-State Lett.

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The bonding strength of low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition ͑PECVD͒ oxides to thermal oxide is studied. Prior to bonding, all CVD oxide wafers are subjected to careful surface preparation including densification, chemical-mechanical polishing, activation, and post-bond annealing to ensure high-quality bonding. All wafers show surface roughness and wafer bow suitable for bonding after the surface preparations. It is found that bonding strength increases upon annealing and saturates beyond 2 h of annealing for the temperature range of 200-300°C. Tetraethyl orthosilicate source PECVD oxide is found to exhibit suitable bonding properties and can be used in applications such as silicon layer transfer.Three-dimensional ͑3D͒ integration, in the form of a vertical stack of several interconnected device layers, has many performance, integration, and cost advantages. 1 Direct Cu-to-Cu wafer bonding 2,3 has been proposed as a method to fabricate 3D structures. In this method, a thinned silicon-on-insulator ͑SOI͒ device layer is bonded to a substrate device wafer in a back-to-face fashion. This requires bonding of the SOI wafer to a top wafer, known as a handle wafer, to assist in SOI wafer handling in subsequent processes followed by SOI wafer etchback from the bottom. The thinned SOI layer is then permanently bonded to the substrate device wafer using Cu as the bonding medium. The bonding between the SOI wafer and the handle wafer is a temporary sacrificial bond, as the handle wafer will be released from the final 3D stack. Hence, this bond has to be strong enough to hold the SOI wafer during subsequent processes. However, the same bond should release readily during SOI thin-film transfer onto the substrate wafer. Epoxy 4 and other adhesives 5 have been investigated, but they are not compatible with the 400°C process temperature during Cu wafer bonding and the chemical attack during SOI wafer etchback. In this paper, we investigate lowtemperature direct oxide wafer bonding for this application.Oxide wafer bonding has been studied and applied extensively for application in SOI wafers 6,7 and microelectromechanical system ͑MEMS͒ 8 fabrication. Most research has concentrated on bonding thermal oxide wafers and silicon wafers that have suitable properties for bonding. In the silicon layer transfer flow described above, the SOI wafer has completed the front-end-of-line ͑FEOL͒ processes and any subsequent high-temperature oxidation is prohibited. In this case, one might have to resort to oxides prepared at low temperature ͑400°C and below͒ by means of chemical vapor deposition ͑CVD͒. 9 However, CVD oxides prepared at low temperature do not possess properties favorable for wafer bonding. In this work, we investigate the necessary surface preparations needed for successful bonding of CVD oxide wafers deposited at low temperature to thermal oxide wafer grown at high temperature for the above application. Bonding strength of the bonded wafer pairs with regards to CVD oxide types, anne...

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“…As described in the next section, pure TMAH, especially at high concentrations (20-25 wt.%), exhibits high undercutting at non-sharp concave and non-h110i etch mask edges on {100} Si surface, while surfactant added TMAH shows minimum undercutting at all types of corners and edges. Figure 3 shows the schematic representation of (Ismail et al 1990;Sanchez et al 1997;Tong and Gosele 1999;Wiegand et al 2000). The room temperature bonded wafers are annealed at 1,050°C for 1 h in an oxygen environment to increase the bond strength.…”

Section: Suspended Structuresmentioning

confidence: 99%

Fabrication methods based on wet etching process for the realization of silicon MEMS structures with new shapes

Pal

Sato

2010

Microsyst Technol

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In this paper, fabrication methods are developed in order to realize the silicon microelectromechanical systems components with new shapes in {100} Si wafers. Fabrication process utilizes wet etching with a single step of photolithography. The silicon etching is carried out in complementary metal oxide semiconductor process compatible pure and surfactant Triton-X-100 [C 14 H 22 O (C 2 H 4 O] n , n = 9-10) added tetramethylammonium hydroxide (TMAH) solutions. The fabricated structures are divided in two categories: fixed and freestanding. The fixed structures are realized in single oxidized silicon wafers, while freestanding are formed in silicon nitride-based silicon on insulator (SOI) wafers. The SOI wafers are prepared by bonding the oxidized and the nitride deposited wafers, followed by thinning and chemical mechanical polishing processes. The etching results such as {100} and {110}Si etch rates, undercutting at rounded concave and sharp convex corners and etched surface morphologies are measured in both pure and Triton added TMAH solutions. Different concentrations of TMAH are used to optimize the etching conditions for desired etched profiles.

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Wafer bonding of silicon wafers covered with various surface layers

Cited by 40 publications

References 9 publications

A Review of Hydrophilic Silicon Wafer Bonding

A Review of Hydrophilic Silicon Wafer Bonding

Low-Temperature Direct CVD Oxides to Thermal Oxide Wafer Bonding in Silicon Layer Transfer

Fabrication methods based on wet etching process for the realization of silicon MEMS structures with new shapes

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