Vorbemerkung

Kümmel, Werner Georg

doi:10.1515/9783111368429.4

Cited by 1 publication

(5 citation statements)

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“…No further decrease was observed when long TMA pulses are used for more than 5 cycles. A reduction in Dit levels can be attributed to the reduction in III-V-oxides at the InGaAs/high-κ interface because of a self-cleaning action of TMA or the effective passivation of TMA by the Al-As bonds as described in literature by many groups (5,7,8,9,10). Assuming this mechanism, the reduction of interface states will not change above a certain amount of TMA/H2O cycles when TMA is not affecting anymore the interface.…”

Section: Discussionmentioning

confidence: 96%

“…However, it is unclear what role the TMA pre-pulse is playing. In the paper by Ahn et al (10), saturating the InGaAs (2x4) reconstructed surface with TMA seems to passivate the As dimers by forming As-Al-As bridge bonds and therefore restoring the As tetrahedral geometry and thereby eliminating the As bond angle strain. This experiment may not be compared to the usual experiments where an ex-situ clean is followed by a long TMA pre-pulse prior to the Al2O3 deposition by ALD.…”

Section: Iii-v Gate Stack Passivation: Interface Versus Oxide Trapsmentioning

confidence: 98%

“…Moreover, simulation work and experimental work has shown that a reduction of Dit can be attributed to the removal of III-V-oxides at the III-V/high-κ interface (1). In addition, several groups have demonstrated the benefit of a long TMA pre-pulse prior to Al2O3 deposition (5,7,8,9,10). However, it is unclear what role the TMA pre-pulse is playing.…”

Section: Iii-v Gate Stack Passivation: Interface Versus Oxide Trapsmentioning

confidence: 99%

“…TMA Pre-pulsing Prior to Al2O3 Deposition TMA pre-pulsing has been reported to improve the interface quality of the In0.53Ga0.47As/high-κ interface (7,8,9,10). The TMA pulse length was changed from the standard pulse length of 0.1 s to 5 s prior to 4 nm of Al2O3 deposition.…”

Section: Improvement Of Interface Traps By Changing the Pretreatmentmentioning

confidence: 99%

“…Reduction of Dit by using TMA and S is widely used in literature (5,7,8,10,11,12,13,14). However, RE-oxides are also being used on III-V for yielding low Dit on InGaAs (16,17).…”

Section: Re-oxides Interfacial Passivation Prior To Al2o3 Deposition ...mentioning

confidence: 99%

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Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

Sioncke¹,

Nyns²,

Ivanov³

et al. 2014

ECS Trans.

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The passivation of the III-V/high-k interface is of key importance in order to bring these materials into the 7 nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons and therefore the mobility will drop and the SS (Subthreshold Slope) will degrade. Additional defects present in the oxide near the III-V interface will generate device instabilities: the targeted amount of oxide traps should be below <1.5E10 /cm2 at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5 nm). However, the oxide trap behavior seems to change only slightly with the ALD process and further improvement of the ALD process is required when introducing the III-V materials into the 7 nm technology node.

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Section: Discussionmentioning

confidence: 96%

Section: Iii-v Gate Stack Passivation: Interface Versus Oxide Trapsmentioning

confidence: 98%

Section: Iii-v Gate Stack Passivation: Interface Versus Oxide Trapsmentioning

confidence: 99%

Section: Improvement Of Interface Traps By Changing the Pretreatmentmentioning

confidence: 99%

“…Reduction of Dit by using TMA and S is widely used in literature (5,7,8,10,11,12,13,14). However, RE-oxides are also being used on III-V for yielding low Dit on InGaAs (16,17).…”

Section: Re-oxides Interfacial Passivation Prior To Al2o3 Deposition ...mentioning

confidence: 99%

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