Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

Abstract

The passivation of the III-V/high-k interface is of key importance in order to bring these materials into the 7 nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons and therefore the mobility will drop and the SS (Subthreshold Slope) will degrade. Additional defects present in the oxide near the III-V interface will generate device instabilities: the targeted amount of oxide traps should be below <1.5E10 /cm2 at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5 nm). However, the oxide trap behavior seems to change only slightly with the ALD process and further improvement of the ALD process is required when introducing the III-V materials into the 7 nm technology node.

On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in IIIV/High-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math> </inline-formula> MOS Stack

“…The gate-stack comprised a 1nm Al2O3 interfacial layer, typically deposited on IIIV channels to prevent the formation of detrimental native interfacial oxides [1,6,14], and 3nm HfO2. The layers were deposited by ALD at 300 °C, and TMAH and HfCl4/H2O were used as precursors for Al2O3 and HfO2, respectively [20]. The gate metal was formed using PVD TiN, while the S/D contacts were formed using Mo/Al.…”

Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

“…The Al2O3 gate stack was deposited by ALD at 300 °C, and TMA and HfCl4/H2O were used as precursors for Al2O3 and HfO2, respectively [19]. For the ASM-IL gate-stack, H2S pretreatment and deposition of the ASM-IL (Inter Layer), LaSiOx, and HfO2 were done in an ASM Pulsar ® 3000 ALD reactor.…”