Vooduu: Verification of Object-Oriented Designs Using UPPAAL

Abstract

Abstract. The Unified Modeling Language (UML) provides sequence diagrams to specify inter-object communication in terms of scenarios. The intra-object behavior is modelled by statechart diagrams. Our tool Vooduu performs an automated consistency check on both views, i.e., it verifies automatically whether a family of UML statecharts modelling a system satisfies a set of communication and timing constraints given as UML sequence diagrams. The front-end of the tool is implemented as a plug-in for a commercial UML tool. For verifying, statecharts and sequence diagrams are translated to the formalism of timed automata. The tool generates temporal logic queries, which depend on an interpretation status for each sequence diagram. The verification is performed by the model checker UPPAAL. The results are retranslated into sequence diagrams. Thus the formal verification machinery is mainly hidden from the user. The tool was applied to a model of the control software of a robot prototype.

State machine flattening, a mapping study and tools assessment

“…90% of the publications illustrate the transformation with examples (Q.1.2), 90% describe the input and output models (Q.1.4), and 80% provide more detailed guidelines. Only [41] and [18] give no example nor guideline. The former…”

Formal specification and verification of real-time systems using Graph Grammars

“…After the translations, the model-checker Uppaal [3] is called to check if the Observer Timed Automaton describes a reachable behavior of the system. Diethers and Hunh [9] propose a similar approach through the Vooduu tool. Nevertheless, these tools restrict the specification of a real-time system.…”

On OO Design Consistency in Iterative Development

“…A model checker is an automatic tool that is able to compare the requirements and design descriptions of a given system. Karsten Diethers and Michael Huhn [7] present a tool for model checking UML designs. Their approach operates by converting UML to finite state automata, checking for errors in the automata and then reporting errors back in UML.…”