2015 IEEE Eighth International Conference on Software Testing, Verification and Validation Workshops (ICSTW) 2015
DOI: 10.1109/icstw.2015.7107408
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State machine flattening, a mapping study and tools assessment

Abstract: International audienceState machine formalisms equipped with hierarchy and parallelism allow to compactly model complex system behaviours. Such models can then be transformed into executable code or inputs for model-based testing and verification techniques. Generated artifacts are mostly flat descriptions of system behaviour. Flattening is thus an essential step of these transformations. To assess the importance of flattening, we have defined and applied a systematic mapping process and 30 publications were f… Show more

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Cited by 7 publications
(2 citation statements)
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References 36 publications
(107 reference statements)
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“…Flattening a model in order to simplify it is a rather common activity. The authors in [13] present flattening transformations for state machines equipped with hierarchy and parallelism, in order to transform models into executable code or inputs for model-based testing and verification techniques.…”
Section: Related Workmentioning
confidence: 99%
“…Flattening a model in order to simplify it is a rather common activity. The authors in [13] present flattening transformations for state machines equipped with hierarchy and parallelism, in order to transform models into executable code or inputs for model-based testing and verification techniques.…”
Section: Related Workmentioning
confidence: 99%
“…It is performed in several existing tools which process various types of statecharts. A recent study on flattening is available at [6].…”
Section: Reachability In Hierarchical Emmtsmentioning
confidence: 99%