Voltage scheduling in the IpARM microprocessor system

Abstract

Microprocessors represent a significant portion of the energy consumed in portable electronic devices. Dynamic Voltage Scaling (DVS) allows a device to reduce energy consumption by lowering its processor speed at run-time, allowing a corresponding reduction in processor voltage and energy. A voltage scheduler determines the appropriate operating voltage by analyzing application constraints and requirements. A complete software implementation, including both applications and the underlying operating system, shows that DVS is effective at reducing the energy consumed without requiring extensive software modification.

Green Operating System: Future Low Power Operating System

“…Till date, processing speed of applications is not fast enough but the number of applications are increasing day by day; so, it is better to switch the processor between different operating modes keeping in mind the trade-off between low power and Voltage scaling and slowing down of frequency has to go hand in hand else the power saving will be an offset by equal increase in execution time, which will lead to no reduction in the total energy. Since, energy is directly proportional to the square of the voltage; reduction of operating voltage can yield considerable energy savings [4]. The central issue with processors whose performance can be changed is how the right level of performance can be obtained.…”

“…We have to think and focus on optimizing the efficiency of the networking hardware and reduce its power consumption. The techniques such as aggregating processor free time [1], Voltage scaling [4] are being implemented for multimedia applications. There is very less work in area of making low operating system with reference to the networking applications.…”

Energy efficiency through burstiness

“…The key idea is to schedule so as to "squeeze out the idle time" in rate-based applications. Several researchers have proposed voltage schedulers for general purpose systems [7,11,28,24]. Lebeck et al [17] explore power-aware page allocation in order to make a more efficient use of memory chips supporting multiple power states, such as the Rambus DRAM chips.…”

Toward the Placement of Power Management Points in Real-Time Applications

“…When setting a new speed, the CPU clock and the voltage fed to the CPU need to be changed, incurring a wide range of delays. For example, the Strong Arm SA-1100 is capable of on-the-fly clock frequency changes in the range of 59MHz to 206MHz where each speed and voltage change incurs a latency of up to 150 µsec [7], while the lpARM processor [9] (a lowpower implementation of the ARM 8 architecture) takes 25 µs for a full swing from 10 MHz to 100 MHz. Another example is the Transmeta TM5400, which is specifically designed for DVS [12].…”

“…Another example is the Transmeta TM5400, which is specifically designed for DVS [12]. Some systems can continue operation while speed and voltage change [9,4], but the frequency continues to vary during the transition period. Some systems stop during steep changes.…”