Managing energy consumption has become vitally important to battery-operated portable and embedded systems. Dynamic voltage scaling (DVS) reduces the processor's dynamic power consumption quadratically at the expense of linearly decreasing the performance. When reducing energy with DVS for real-time systems, one must consider the performance penalty to ensure that deadlines can be met. In this paper, we introduce a novel collaborative approach between the compiler and the operating system (OS) to reduce energy consumption. We use the compiler to annotate an application's source code with path-dependent information called power-management hints (PMHs). This fine-grained information captures the temporal behavior of the application, which varies by executing different paths. During program execution, the OS periodically changes the processor's frequency and voltage based on the temporal information provided by the PMHs. These speed adaptation points are called power-management points (PMPs). We evaluate our scheme using three embedded applications: a video decoder, automatic target recognition, and a sub-band tuner. Our scheme shows an energy reduction of up to 57% over no power-management and up to 32% over a static power-management scheme. We compare our scheme to other schemes that solely utilize PMPs for power-management and show experimentally that our scheme achieves more energy savings. We also analyze the advantages and disadvantages of our approach relative to another compiler-directed scheme.

Dynamically changing CPU voltage and frequency have been shown to greatly save the processor energy. These adjustments can be done at specific power management points (PMPs), which are not without overheads. In this work we study the effect of different overheads on both time and energy; these can be seen as the overhead of computing the new speed, and then the overhead of dynamically adjusting the speed. We propose a theoretical solution for choosing the granularity of inserting PMPs in a program taking into consideration such overheads. We validate our theoretical results and show that the accuracy of the theoretical model is between zero and five management points of simulation results.

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Reducing device energy has become one of the most important challenges to embedded systems designers. Processors with dynamic voltage scaling permit trading performance for reduced energy consumption as a program executes. In this paper, we rst present a novel hybrid scheme that uses dynamic voltage scaling to adjust the performance o f embedded applications to reduce energy consumption while also meeting time constraints. Our ne-grained a p p r oach uses the compiler to insert power management hints in the application c ode. These hints convey path-speci c runtime information about the program's progress to power management p o i n ts invoked b y t h e o p erating system that adjust processor performance. Second, we present an algorithm for inserting power management hints along di erent program paths. Finally, we experimentally evaluate our approach and show that signi cant energy reduction can be achieved. On two embedded applications, MPEG movie decoding and automatic target recognition, our scheme reduces energy by up to 79% over no power management and by up to 50% over static power management. We also experimentally demonstrate that our scheme achieves more energy savings compared to two purely compiler-directed schemes.

Abstract-The main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a power-aware cached-dynamic-RAM (PA-CDRAM) organization that integrates a moderately sized cache directly into a memory chip. We use this near-memory cache to turn a memory bank off immediately after it is accessed to reduce power consumption. We modify the operation and structure of CDRAM with the goal of reducing energy consumption while retaining the performance advantage for which CDRAM was originally proposed. In this paper, we describe our PA-CDRAM organization and show how to incorporate it into the Rambus memory. We evaluate the approach using a cycle-accurate processor and memory simulator. Our results show that PA-CDRAM achieves up to 84 percent (28 percent on the average) improvement in the energy-delay product and up to 76 percent (19 percent on the average) savings in energy when compared to a time-out power management technique.Index Terms-Memory design, power management, energy-aware systems, memory power management, cached DRAM.

Managing energy consumption has become vitally important to battery-operated portable and embedded systems. Dynamic voltage scaling (DVS) reduces the processor's dynamic power consumption quadratically at the expense of linearly decreasing the performance. When reducing energy with DVS for real-time systems, one must consider the performance penalty to ensure that deadlines can be met. In this paper, we introduce a novel collaborative approach between the compiler and the operating system (OS) to reduce energy consumption. We use the compiler to annotate an application's source code with path-dependent information called power-management hints (PMHs). This fine-grained information captures the temporal behavior of the application, which varies by executing different paths. During program execution, the OS periodically changes the processor's frequency and voltage based on the temporal information provided by the PMHs. These speed adaptation points are called power-management points (PMPs). We evaluate our scheme using three embedded applications: a video decoder, automatic target recognition, and a sub-band tuner. Our scheme shows an energy reduction of up to 57% over no power-management and up to 32% over a static power-management scheme. We compare our scheme to other schemes that solely utilize PMPs for power-management and show experimentally that our scheme achieves more energy savings. We also analyze the advantages and disadvantages of our approach relative to another compiler-directed scheme.

Reducing device energy has become one of the most important challenges to embedded systems designers. Processors with dynamic voltage scaling permit trading performance for reduced energy consumption as a program executes. In this paper, we rst present a novel hybrid scheme that uses dynamic voltage scaling to adjust the performance o f embedded applications to reduce energy consumption while also meeting time constraints. Our ne-grained a p p r oach uses the compiler to insert power management hints in the application c ode. These hints convey path-speci c runtime information about the program's progress to power management p o i n ts invoked b y t h e o p erating system that adjust processor performance. Second, we present an algorithm for inserting power management hints along di erent program paths. Finally, we experimentally evaluate our approach and show that signi cant energy reduction can be achieved. On two embedded applications, MPEG movie decoding and automatic target recognition, our scheme reduces energy by up to 79% over no power management and by up to 50% over static power management. We also experimentally demonstrate that our scheme achieves more energy savings compared to two purely compiler-directed schemes.