Voltage pulse stress effect on gate stack TDDB distributions at nanometric scale: Consequence on aging by ESD

Nanoscale Characterization of High-K/IL Gate Stack TDDB Distributions After High-Field Prestress Pulses

“…Thanks to this area scaling effect, the breakdown voltage (V BD ) is sufficiently high at nanometric scale [15] to measure the impact of preset voltage pulses with higher amplitude or longer duration than at a device scale without leading to breakdown. In a previous study we have investigated the degradation due to pre-stress pulses of the SiON interfacial layer alone by C-AFM under ultra-high vacuum [16]. In this paper, we used the same method to study the impact of voltage pulses on bimodal TDDB distributions obtained on a High-k/IL bilayer gate oxide stack.…”