VLSI Programming of Asynchronous Circuits for Low Power

Berkel, Kees van; Rem, Martin

doi:10.1007/978-1-4471-3575-3_4

Cited by 18 publications

(25 citation statements)

References 15 publications

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“…• Peephole optimisations: this technique is based on the identification of a pattern of components that can be replaced with an faster alternative [2]- [4].…”

Section: Introductionmentioning

confidence: 99%

Description-Level Optimisation of Synthesisable Asynchronous Circuits

Tarazona

Edwards

Bardsley

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-The syntax-directed synthesis paradigm has shown to be a powerful synthesis approach. However, its control-driven nature results in significant performance overhead. Some methods to reduce this overhead include peephole optimisations, control resynthesis and component optimisations. This work explores new methods of improving the performance of syntax-directed synthesised asynchronous circuits, using the Balsa synthesis system as the research framework. This includes investigating description styles and the usage of language constructs that exploit the directness of the synthesis method to obtain more concurrent and faster circuits. The techniques and optimisations presented here has been tested in a set of non-trivial examples including a 32-bit processor, a Viterbi decoder, and a channel-sliced wormhole router.

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“…• Peephole optimisations: this technique is based on the identification of a pattern of components that can be replaced with an faster alternative [2]- [4].…”

Section: Introductionmentioning

confidence: 99%

Description-Level Optimisation of Synthesisable Asynchronous Circuits

Tarazona

Edwards

Bardsley

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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“…Compared to other asynchronous circuit styles such as those based on single-rail data encoding [22], these asynchronous circuits require few timing requirements: arbitrary gate and wire delays are allowed as long as weak timing constraints are satisfied at wire fanout points (details are provided in Section 2). However, although both DIMS and NCL approaches result in highly-robust asynchronous circuits, they suffer from large area and latency overhead.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Jeong

Nowick

2007

2007 Asia and South Pacific Design Automation Conference

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Abstract-As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

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“…The feed-back transistors N3 and P3 are, as usual, of minimum size, and N6 and P6 have a normal size to achieve load driving capability of the previous circuits. 5 Results of the Tests Figure 7 shows the energy dissipation versus the propagation delay for the three C-element implementations with a fan-out of 3 inverters under the rst test. The size of the C-element gate increases for each curve from the right hand side of the graph toward the top of the graph.…”

Section: C-element Implementationsmentioning

confidence: 99%

“…Martin and has been used in the Caltech asynchronous microprocessor [2] and an asynchronous, low-power version of the ARM developed at Manchester University [3]; a third implementation has been introduced by K . V an Berkel and is being used in the TANGRAM silicon compiler for low-power design at Philips Research Laboratories [5]. The dierent implementations are examined in two different setups.…”

Section: Introductionmentioning

confidence: 99%

A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element

Shams¹,

Ebergen²,

Elmasry³

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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One of the most frequently used primitives in asynchronous control circuits is the C-element. The three most popular CMOS implementations of the C-element are compared with respect to energy-eciency, delay, and area, with an emphasis on energy. The three implementations have been introduced by Sutherland, Martin, and Van Berkel. We show that in a typical environment, Van Berkel's implementation is superior to the other implementations with respect to energy consumption and area, for the same delay.

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VLSI Programming of Asynchronous Circuits for Low Power

Cited by 18 publications

References 15 publications

Description-Level Optimisation of Synthesisable Asynchronous Circuits

Description-Level Optimisation of Synthesisable Asynchronous Circuits

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element

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